公开(公告)号：US4729063A

公开(公告)日：1988-03-01

申请号：US831279

申请日：1986-02-20

申请人： Ryuichi Matsuo ,  Masahide Kaneko ,  Hirokazu Harima

发明人： Ryuichi Matsuo ,  Masahide Kaneko ,  Hirokazu Harima

IPC分类号： H01L21/3205 ,  H01L23/52 ,  H01L23/522 ,  H05K1/14

CPC分类号： H01L23/5226 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265

摘要： A plastic molded semiconductor integrated circuit device, includes: a semiconductor substrate in which circuit elements are fabricated, metal wirings for transmitting the power supply voltage or signals of internal circuits provided on the semiconductor substrate via an insulating film, a plurality of apertures produced at portions of the insulating film directly below the metal wirings, and a nail section provided integrally with the metal wiring in the aperture, wherein the nail section is provided without being electrically connected with any of the circuit elements or the other metal wirings.

摘要翻译： 一种塑料模制半导体集成电路器件，包括：其中制造电路元件的半导体衬底，用于透过绝缘膜传输设置在半导体衬底上的电源电压或内部电路的信号的金属配线，在部分产生的多个孔 直接位于金属布线下方的绝缘膜，以及与孔中的金属布线一体设置的指甲部分，其中指甲部分设置成不与任何电路元件或其它金属布线电连接。

公开(公告)号：US4651186A

公开(公告)日：1987-03-17

申请号：US438336

申请日：1982-11-01

申请人： Makoto Yamamoto ,  Tsuyoshi Toyama ,  Hirokazu Harima ,  Ryo Ando

发明人： Makoto Yamamoto ,  Tsuyoshi Toyama ,  Hirokazu Harima ,  Ryo Ando

IPC分类号： H01L29/788 ,  H01L29/78 ,  H01L27/02 ,  H01L29/04 ,  H01L29/34

CPC分类号： H01L29/7881

摘要： A field effect transistor comprises a source region (42) annularly formed to encompass and spaced apart from a drain region (41), whereby a second channel region is formed between the drain region and the source region in the vicinity of the former, while a first channel region is formed in the remaining area thereof, an annular first gate (43) formed bridging above the first channel region and the source region, a second annular gate (45) formed bridging above the first gate and the drain region, and an isolating film (47) formed contiguous to the source region at the side opposite to the channel region. As a result any region is eliminated where the channel region in the vicinity of the drain side end of the first gate (43) is in contact with the isolating film (47). Accordingly, no withstand voltage is restricted thereby and the withstand voltage of the field effect transistor is considerably enhanced.

摘要翻译： 场效应晶体管包括环形地形成为包围并与漏区（41）间隔开的源极区域（42），由此在漏极区域和在源极区域附近的源极区域之间形成第二沟道区域，而 在其剩余区域中形成有第一沟道区，桥接在第一沟道区和源极区之上的环形第一栅极（43），形成在第一栅极和漏极区上方桥接的第二环形栅极（45），以及 隔离膜（47），其形成在与沟道区相对的一侧与源极区邻接。 结果，在第一栅极（43）的漏极侧端部附近的沟道区域与隔离膜（47）接触的情况下，消除了任何区域。 因此，不会限制耐压，并且显着提高了场效应晶体管的耐受电压。