Information processing apparatus, information processing method, and information processing program
    4.
    发明授权
    Information processing apparatus, information processing method, and information processing program 有权
    信息处理装置,信息处理方法和信息处理程序

    公开(公告)号:US08564719B2

    公开(公告)日:2013-10-22

    申请号:US12418918

    申请日:2009-04-06

    IPC分类号: H04N7/01 H04N11/20 H04N5/46

    摘要: An information processing apparatus that has a frame buffer that stores an input video signal, that loads a video signal at an asynchronous timing with the video signal input from the frame buffer and then that I/P-converts the loaded video signal from an interlaced signal into a progressive signal includes: pulldown determination means that determines whether the input video signal is subjected to a process of skipping or repeating a source video signal through a pulldown process; and control means that, when it is determined that the input video signal is subjected to the process of skipping or repeating, controls a process of skipping or repeating the loaded video signal to obtain a pulldown pattern supported at an I/P conversion side at which the I/P-conversion is performed, when the loaded video signal is converted from an interlaced signal into a progressive signal.

    摘要翻译: 一种信息处理装置,具有存储输入视频信号的帧缓冲器,该帧缓冲器以异步定时加载从帧缓冲器输入的视频信号的视频信号,然后对来自隔行扫描信号的加载视频信号进行I / P转换 逐行信号包括:下拉确定装置,其确定输入视频信号是否经过下拉处理跳过或重复源视频信号的处理; 并且控制意味着当确定输入视频信号经过跳过或重复的处理时,控制跳过或重复加载的视频信号的处理以获得在I / P转换侧支持的下拉模式,其中, 当加载的视频信号从隔行信号转换成逐行信号时,执行I / P转换。

    INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM
    5.
    发明申请
    INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM 有权
    信息处理设备,信息处理方法和信息处理程序

    公开(公告)号:US20090251598A1

    公开(公告)日:2009-10-08

    申请号:US12418918

    申请日:2009-04-06

    IPC分类号: H04N11/20 H04N7/01

    摘要: An information processing apparatus that has a frame buffer that stores an input video signal, that loads a video signal at an asynchronous timing with the video signal input from the frame buffer and then that I/P-converts the loaded video signal from an interlaced signal into a progressive signal includes: pulldown determination means that determines whether the input video signal is subjected to a process of skipping or repeating a source video signal through a pulldown process; and control means that, when it is determined that the input video signal is subjected to the process of skipping or repeating, controls a process of skipping or repeating the loaded video signal to obtain a pulldown pattern supported at an I/P conversion side at which the I/P-conversion is performed, when the loaded video signal is converted from an interlaced signal into a progressive signal.

    摘要翻译: 一种信息处理装置,具有存储输入视频信号的帧缓冲器,该帧缓冲器以异步定时加载从帧缓冲器输入的视频信号的视频信号,然后对来自隔行扫描信号的加载视频信号进行I / P转换 逐行信号包括:下拉确定装置,其确定输入视频信号是否经过下拉处理跳过或重复源视频信号的处理; 并且控制意味着当确定输入视频信号经过跳过或重复的处理时,控制跳过或重复加载的视频信号的处理以获得在I / P转换侧支持的下拉模式,其中, 当加载的视频信号从隔行信号转换成逐行信号时,执行I / P转换。

    Program and information processing method
    6.
    发明授权
    Program and information processing method 失效
    程序和信息处理方法

    公开(公告)号:US07331046B2

    公开(公告)日:2008-02-12

    申请号:US10854665

    申请日:2004-05-26

    IPC分类号: G06F9/44

    CPC分类号: G06F9/4403 G06F8/65

    摘要: A program of the present invention is compatible with a plurality of system configurations. When a process jumps to a bootstrap body, CPU configuration and initialization of a timer and a data cache are performed. When the process is not executed on a cache RAM or when the process is executed in an external mode or a ROMless state, data is copied from ROM to RAM, and then the process jumps to a cache RAM area. Then, initialization of a stack, setting of an interrupt vector, and initialization of a heap are sequentially performed. The present invention can be applied to an apparatus for developing a system LSI.

    摘要翻译: 本发明的程序与多个系统配置兼容。 当进程跳转到引导主体时,执行CPU配置和初始化定时器和数据高速缓存。 当处理不在高速缓存RAM上执行时,或者当处理在外部模式或无ROM状态下执行时,数据从ROM复制到RAM,然后进程跳转到高速缓存RAM区域。 然后,依次执行堆栈的初始化,中断向量的设置和堆的初始化。 本发明可以应用于系统LSI的开发装置。

    Data stream buffer control using reference time and decoding time
    7.
    发明授权
    Data stream buffer control using reference time and decoding time 有权
    数据流缓存控制使用参考时间和解码时间

    公开(公告)号:US08359413B2

    公开(公告)日:2013-01-22

    申请号:US12706126

    申请日:2010-02-16

    IPC分类号: G06F3/00 G06F15/16

    摘要: A buffer control device includes a reference time generation unit configured to generate a reference time based on time information included in a data stream input, a buffer configured to receive an encoded data extracted from the data stream, store the encoded data, and output the encoded data at a decoding time or a reproducing time of the encoded data, and a control unit configured to control an input of the encoded data to the buffer based on a relativity between the decoding time or the reproducing time of the encoded data and the reference time.

    摘要翻译: 一种缓冲器控制装置,包括:基准时间生成部,其基于包含在数据流输入中的时间信息生成基准时刻;缓冲器,被配置为接收从数据流提取的编码数据,存储编码数据,并输出编码数据 数据在编码数据的解码时刻或再现时间,以及控制单元,被配置为基于编码数据的解码时间或再现时间与参考时间之间的相对性来控制对缓冲器的编码数据的输入 。

    Program and information processing method
    8.
    发明申请
    Program and information processing method 失效
    程序和信息处理方法

    公开(公告)号:US20050015582A1

    公开(公告)日:2005-01-20

    申请号:US10854665

    申请日:2004-05-26

    IPC分类号: G06F9/445 G06F9/00

    CPC分类号: G06F9/4403 G06F8/65

    摘要: A program of the present invention is compatible with a plurality of system configurations. When a process jumps to a bootstrap body, CPU configuration and initialization of a timer and a data cache are performed. When the process is not executed on a cache RAM or when the process is executed in an external mode or a ROMless state, data is copied from ROM to RAM, and then the process jumps to a cache RAM area. Then, initialization of a stack, setting of an interrupt vector, and initialization of a heap are sequentially performed. The present invention can be applied to an apparatus for developing a system LSI.

    摘要翻译: 本发明的程序与多个系统配置兼容。 当进程跳转到引导主体时,执行CPU配置和初始化定时器和数据高速缓存。 当处理不在高速缓存RAM上执行时,或者当处理在外部模式或无ROM状态下执行时,数据从ROM复制到RAM,然后进程跳转到高速缓存RAM区域。 然后,依次执行堆栈的初始化,中断向量的设置和堆的初始化。 本发明可以应用于系统LSI的开发装置。

    BUFFER CONTROL DEVICE, BUFFER CONTROL METHOD, AND PROGRAM
    9.
    发明申请
    BUFFER CONTROL DEVICE, BUFFER CONTROL METHOD, AND PROGRAM 有权
    缓冲器控制装置,缓冲器控制方法和程序

    公开(公告)号:US20100211706A1

    公开(公告)日:2010-08-19

    申请号:US12706126

    申请日:2010-02-16

    IPC分类号: G06F5/00

    摘要: A buffer control device includes a reference time generation unit configured to generate a reference time based on time information included in a data stream input, a buffer configured to receive an encoded data extracted from the data stream, store the encoded data, and output the encoded data at a decoding time or a reproducing time of the encoded data, and a control unit configured to control an input of the encoded data to the buffer based on a relativity between the decoding time or the reproducing time of the encoded data and the reference time.

    摘要翻译: 一种缓冲器控制装置,包括:基准时间生成部,其基于包含在数据流输入中的时间信息生成基准时刻;缓冲器,被配置为接收从数据流提取的编码数据,存储编码数据,并输出编码数据 数据在编码数据的解码时刻或再现时间,以及控制单元,被配置为基于编码数据的解码时间或再现时间与参考时间之间的相对性来控制对缓冲器的编码数据的输入 。