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公开(公告)号:US08778710B2
公开(公告)日:2014-07-15
申请号:US13682371
申请日:2012-11-20
发明人: Byeong-Jae Ahn
CPC分类号: H01L33/005 , H01L21/02104 , H01L21/02697 , H01L27/1214 , H01L27/124 , H01L27/1288 , H01L27/3237
摘要: A display substrate is provided that can prevent the opening of an upper conduction layer. The display substrate comprises a semiconductor layer pattern formed on a substrate, a data interconnection pattern formed on the semiconductor layer pattern, a protection layer formed on the substrate and the data interconnection pattern, contact holes formed on the substrate to expose at least a portion of an upper surface of the semiconductor pattern and at least a portion of an upper surface of the data interconnection pattern, and contact electrodes formed in the contact holes to be in contact with the exposed upper surfaces of the data interconnection pattern and the semiconductor layer pattern.
摘要翻译: 提供了能够防止上导电层开放的显示基板。 显示基板包括形成在基板上的半导体层图案,形成在半导体层图案上的数据互连图案,形成在基板上的保护层和数据互连图案,形成在基板上的接触孔,以暴露至少一部分 半导体图案的上表面和数据互连图案的上表面的至少一部分,以及形成在接触孔中的接触电极,以与数据互连图案和半导体层图案的暴露的上表面接触。
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公开(公告)号:US09844155B2
公开(公告)日:2017-12-12
申请号:US14312857
申请日:2014-06-24
发明人: Byeong-Jae Ahn , Ju-Hyeon Baek , Dong-Wuuk Seo , Bong-Jun Lee
IPC分类号: H05K5/00 , H05K5/02 , G02F1/1333
CPC分类号: H05K5/02 , G02F1/133308 , G02F2001/13332 , G02F2001/133328 , G02F2201/46
摘要: A display panel includes a first substrate, a second substrate which faces the first substrate, is smaller than the first substrate so that an edge of the first substrate is exposed in a plan view, a fixing member disposed on the exposed edge of the first substrate, and a bonding member disposed between the first substrate and the fixing member.
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公开(公告)号:US09601075B2
公开(公告)日:2017-03-21
申请号:US14319233
申请日:2014-06-30
发明人: Bong-Jun Lee , Ji-Young Jeong , Ju-Hyeon Baek , Dong-Wuuk Seo , Byeong-Jae Ahn
IPC分类号: G06F1/00 , G09G3/36 , G02F1/1335 , G02F1/1333
CPC分类号: G09G3/3685 , G02F1/133512 , G02F1/133514 , G02F2001/133388 , G09G2310/0283 , Y10T29/49117
摘要: A display panel includes a plurality of pixels disposed in an active area and arranged substantially in a matrix form including a pixel row and a pixel column, a first gate line disposed adjacent to a first side n of the pixel row and connected to a first pixel in the pixel row, a second gate line disposed adjacent to a second side of the pixel row and connected to a second pixel in the pixel row, a plurality of data lines crossing the first and second gate lines, where the pixels in a pair of adjacent pixel columns are connected to a same data line, and a blocking pattern which overlaps a pixel column disposed in an end portion of the active area.
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