公开(公告)号：US09082795B2

公开(公告)日：2015-07-14

申请号：US14477587

申请日：2014-09-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung Lee ,  Chan Woo Yang ,  Seung-Ho Jung ,  Doo Na Kim ,  Bo Sung Kim ,  Eun Hye Park ,  June Whan Choi

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/66 ,  H01B1/06 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01B1/06 ,  H01L21/02565 ,  H01L21/02628 ,  H01L29/7869

Abstract: A thin film transistor substrate according to an exemplary embodiment of the present invention includes a semiconductor layer including metal disposed on an insulating substrate, a gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode overlapping the semiconductor layer, wherein the metal in the semiconductor layer comprises indium (In), zinc (Zn), and tin (Sn), and a molar ratio ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] × 100 ) of indium (In) to the metals in the semiconductor layer is less than about 20%, and more specifically, the molar ratio ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] × 100 ) of indium (In) of the metals in the semiconductor layer is about 5% to about 13%.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管基板包括：半导体层，包括设置在绝缘基板上的金属，与半导体层重叠的栅极电极以及与半导体层重叠的源电极和漏电极，其中金属 在半导体层中包含铟（In），锌（Zn）和锡（Sn），摩尔比（R，R⁡[mol⁢％] = [In] [In + Zn + Sn]×100） 对于半导体层中的金属，铟（In）的含量小于约20％，更具体地说，摩尔比（R，R⁡[mol·⁢％] = [In] [In + Zn + Sn]×100 ）的半导体层中的金属的In（In）为约5％至约13％。

公开(公告)号：US09287297B2

公开(公告)日：2016-03-15

申请号：US14486620

申请日：2014-09-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sho Yeon Kim ,  Hyun Kim ,  Eun Hye Park ,  Byung Hwan Chu ,  Seung-Ha Choi

IPC: H01L31/036 ,  H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a first connection member of a gate driver region and a gate electrode of a display area, a gate insulating layer disposed on the substrate and having a first contact hole exposing the first connection member, a semiconductor layer disposed on a region of the gate insulating layer, a data line disposed on the gate insulating layer and the semiconductor layer and including a drain electrode, a source electrode, and a second connection member connected to the first connection member through the first contact hole, a passivation layer disposed on the data line, the source electrode, the drain electrode, and the second connection member, and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode. A horizontal width of the first contact hole ranges from 1 to 2 μm.

Abstract translation: 薄膜晶体管阵列面板包括：栅极线，其设置在基板上，并且包括栅极驱动器区域的第一连接构件和显示区域的栅极电极，栅极绝缘层，设置在所述基板上，并且具有暴露于所述第一接触孔 所述第一连接构件，设置在所述栅极绝缘层的区域上的半导体层，设置在所述栅极绝缘层和所述半导体层上的数据线，并且包括漏电极，源电极和连接到所述第一连接构件的第二连接构件 连接构件，通过第一接触孔，设置在数据线上的钝化层，源电极，漏电极和第二连接构件，以及设置在钝化层上并电连接到漏电极的像素电极。 第一接触孔的水平宽度为1〜2μm。

公开(公告)号：US09455278B2

公开(公告)日：2016-09-27

申请号：US15053807

申请日：2016-02-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sho Yeon Kim ,  Hyun Kim ,  Eun Hye Park ,  Byung Hwan Chu ,  Seung-Ha Choi

IPC: H01L31/036 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a first connection member of a gate driver region and a gate electrode of a display area, a gate insulating layer disposed on the substrate and having a first contact hole exposing the first connection member, a semiconductor layer disposed on a region of the gate insulating layer, a data line disposed on the gate insulating layer and the semiconductor layer and including a drain electrode, a source electrode, and a second connection member connected to the first connection member through the first contact hole, a passivation layer disposed on the data line, the source electrode, the drain electrode, and the second connection member, and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode. A horizontal width of the first contact hole ranges from 1 to 2 μm.

公开(公告)号：US08853687B2

公开(公告)日：2014-10-07

申请号：US13679910

申请日：2012-11-16

Applicant: Samsung Display Co., Ltd.

Inventor： Doo Hyoung Lee ,  Chan Woo Yang ,  Seung-Ho Jung ,  Doo Na Kim ,  Bo Sung Kim ,  Eun Hye Park

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/66 ,  H01B1/06

CPC classification number: H01L29/66969 ,  H01B1/06 ,  H01L21/02565 ,  H01L21/02628 ,  H01L29/7869

Abstract: A thin film transistor substrate according to an exemplary embodiment of the present invention includes a semiconductor layer including metal disposed on an insulating substrate, a gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode overlapping the semiconductor layer, wherein the metal in the semiconductor layer comprises indium (In), zinc (Zn), and tin (Sn), and a molar ratio ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] × 100 ) of indium (In) to the metals in the semiconductor layer is less than about 20%, and more specifically, the molar ratio (R, ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] / 100 ) of indium (In) of the metals in the semiconductor layer is about 5% to about 13%.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管基板包括：半导体层，包括设置在绝缘基板上的金属，与半导体层重叠的栅极电极以及与半导体层重叠的源电极和漏电极，其中金属 在半导体层中包含铟（In），锌（Zn）和锡（Sn），摩尔比（R，R⁡[mol⁢％] = [In] [In + Zn + Sn]×100） 对于半导体层中的金属，铟（In）的含量小于约20％，更具体地，摩尔比（R，（R，R⁡[mol⁢％] = [In] [In + Zn + Sn 半导体层中的金属的In（In）的比例为约5％〜13％。