公开(公告)号：US20150044817A1

公开(公告)日：2015-02-12

申请号：US14521043

申请日：2014-10-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Wood Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L29/66 ,  H01L21/477 ,  H01L21/441 ,  H01L21/02 ,  H01L21/385

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

公开(公告)号：US20180040739A1

公开(公告)日：2018-02-08

申请号：US15662502

申请日：2017-07-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SUNG WOOK WOO ,  Chang Ho Lee ,  Kyung Lae Rho ,  Doo Hyoung Lee ,  Sung Chan Jo ,  Sang Woo Sohn ,  Sang Won Shin ,  Soo Im Jeong ,  Chang Yong Jeong

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/10 ,  H01L29/04

CPC classification number: H01L29/78693 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/247 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A transistor includes a gate electrode, a semiconductor layer overlapping the gate electrode, the semiconductor layer including an oxide semiconductor, and a source electrode and a drain electrode spaced apart from the source electrode, wherein the source and drain electrodes are connected to the semiconductor layer. The semiconductor layer includes a plurality of layers, wherein a crystallinity of a layer of the plurality of layers of the semiconductor layer is a ratio of a crystalline oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer, to an amorphous oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer. A first layer of the plurality of layers of the semiconductor layer has a different crystallinity with respect to a second layer of the plurality of layers of the semiconductor layer.

公开(公告)号：US10546959B2

公开(公告)日：2020-01-28

申请号：US15662502

申请日：2017-07-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung Wook Woo ,  Chang Ho Lee ,  Kyung Lae Rho ,  Doo Hyoung Lee ,  Sung Chan Jo ,  Sang Woo Sohn ,  Sang Won Shin ,  Soo Im Jeong ,  Chang Yong Jeong

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/24 ,  H01L29/10

Abstract: A transistor includes a gate electrode, a semiconductor layer overlapping the gate electrode, the semiconductor layer including an oxide semiconductor, and a source electrode and a drain electrode spaced apart from the source electrode, wherein the source and drain electrodes are connected to the semiconductor layer. The semiconductor layer includes a plurality of layers, wherein a crystallinity of a layer of the plurality of layers of the semiconductor layer is a ratio of a crystalline oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer, to an amorphous oxide semiconductor, included in the layer of the plurality of layers of the semiconductor layer. A first layer of the plurality of layers of the semiconductor layer has a different crystallinity with respect to a second layer of the plurality of layers of the semiconductor layer.

公开(公告)号：US09082795B2

公开(公告)日：2015-07-14

申请号：US14477587

申请日：2014-09-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung Lee ,  Chan Woo Yang ,  Seung-Ho Jung ,  Doo Na Kim ,  Bo Sung Kim ,  Eun Hye Park ,  June Whan Choi

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/66 ,  H01B1/06 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01B1/06 ,  H01L21/02565 ,  H01L21/02628 ,  H01L29/7869

Abstract: A thin film transistor substrate according to an exemplary embodiment of the present invention includes a semiconductor layer including metal disposed on an insulating substrate, a gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode overlapping the semiconductor layer, wherein the metal in the semiconductor layer comprises indium (In), zinc (Zn), and tin (Sn), and a molar ratio ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] × 100 ) of indium (In) to the metals in the semiconductor layer is less than about 20%, and more specifically, the molar ratio ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] × 100 ) of indium (In) of the metals in the semiconductor layer is about 5% to about 13%.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管基板包括：半导体层，包括设置在绝缘基板上的金属，与半导体层重叠的栅极电极以及与半导体层重叠的源电极和漏电极，其中金属 在半导体层中包含铟（In），锌（Zn）和锡（Sn），摩尔比（R，R⁡[mol⁢％] = [In] [In + Zn + Sn]×100） 对于半导体层中的金属，铟（In）的含量小于约20％，更具体地说，摩尔比（R，R⁡[mol·⁢％] = [In] [In + Zn + Sn]×100 ）的半导体层中的金属的In（In）为约5％至约13％。

公开(公告)号：US11621312B2

公开(公告)日：2023-04-04

申请号：US17089246

申请日：2020-11-04

Applicant: Samsung Display Co., LTD.

Inventor： Sang Hyung Lim ,  Jee Hoon Kim ,  Mi Hyang Sheen ,  Jin Ho Jang ,  Myeong Kyu Park ,  Na Ri Ahn ,  Hui Won Yang ,  Doo Hyoung Lee

IPC: H01L27/32 ,  H01L51/52

Abstract: A display device includes a first conductive pattern on a substrate, a first insulating layer on the first conductive pattern, a semiconductor pattern on the first insulating layer, a second insulating layer on the first insulating layer and the semiconductor pattern, and a second conductive pattern on the second insulating layer. A first edge of the first conductive pattern faces a second edge of the second conductive pattern, the first conductive pattern does not overlap the second conductive pattern in an area where the first edge faces the second edge, the semiconductor pattern is in the area where the first edge faces the second edge, the second conductive pattern overlaps the second insulating layer, and the second insulating layer includes a third edge protruding from the second edge of the second conductive pattern.

公开(公告)号：US20160300950A1

公开(公告)日：2016-10-13

申请号：US14887483

申请日：2015-10-20

Applicant: Samsung Display Co., Ltd.

Inventor： Hyeon Jun LEE ,  Ki Won Kim ,  Yoo Ho Kim ,  Joon Geol Kim ,  Doo Hyoung Lee

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L21/4763 ,  H01L29/22 ,  H01L29/66 ,  H01L21/44 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L21/44 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1259 ,  H01L29/22 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78618

Abstract: A thin film transistor array panel includes a gate line disposed on a substrate, the gate line including a gate electrode, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the substrate, the semiconductor layer including an oxide semiconductor, a data line disposed on the substrate and crossing the gate line, a data line layer including a source electrode connected to the data line and a drain electrode facing the source electrode, and a passivation layer covering the source electrode and the drain electrode. The data line layer includes copper or a copper alloy, and the semiconductor layer includes a copper doped oxide semiconductor. A content of copper doped on the oxide semiconductor is 0.2% to 0.82%.

Abstract translation: 薄膜晶体管阵列面板包括设置在基板上的栅极线，栅极线包括栅极电极，设置在栅电极上的栅极绝缘层，设置在基板上的半导体层，包括氧化物半导体的半导体层， 数据线，设置在基板上并与栅极线交叉;数据线层，包括连接到数据线的源电极和面对源电极的漏极，以及覆盖源电极和漏电极的钝化层。 数据线层包括铜或铜合金，并且半导体层包括掺铜氧化物半导体。 氧化物半导体上掺杂的铜的含量为0.2〜0.82％。

公开(公告)号：US09406785B2

公开(公告)日：2016-08-02

申请号：US14521043

申请日：2014-10-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L21/441 ,  H01L21/02 ,  H01L21/385 ,  H01L29/66 ,  H01L29/786 ,  H01L21/477

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

公开(公告)号：US08895977B2

公开(公告)日：2014-11-25

申请号：US13673195

申请日：2012-11-09

Applicant: Samsung Display Co., Ltd.

Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L21/786 ,  H01L29/786 ,  H01L21/385

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

公开(公告)号：US08853687B2

公开(公告)日：2014-10-07

申请号：US13679910

申请日：2012-11-16

Applicant: Samsung Display Co., Ltd.

Inventor： Doo Hyoung Lee ,  Chan Woo Yang ,  Seung-Ho Jung ,  Doo Na Kim ,  Bo Sung Kim ,  Eun Hye Park

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/66 ,  H01B1/06

CPC classification number: H01L29/66969 ,  H01B1/06 ,  H01L21/02565 ,  H01L21/02628 ,  H01L29/7869

Abstract: A thin film transistor substrate according to an exemplary embodiment of the present invention includes a semiconductor layer including metal disposed on an insulating substrate, a gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode overlapping the semiconductor layer, wherein the metal in the semiconductor layer comprises indium (In), zinc (Zn), and tin (Sn), and a molar ratio ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] × 100 ) of indium (In) to the metals in the semiconductor layer is less than about 20%, and more specifically, the molar ratio (R, ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] / 100 ) of indium (In) of the metals in the semiconductor layer is about 5% to about 13%.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管基板包括：半导体层，包括设置在绝缘基板上的金属，与半导体层重叠的栅极电极以及与半导体层重叠的源电极和漏电极，其中金属 在半导体层中包含铟（In），锌（Zn）和锡（Sn），摩尔比（R，R⁡[mol⁢％] = [In] [In + Zn + Sn]×100） 对于半导体层中的金属，铟（In）的含量小于约20％，更具体地，摩尔比（R，（R，R⁡[mol⁢％] = [In] [In + Zn + Sn 半导体层中的金属的In（In）的比例为约5％〜13％。