公开(公告)号：US20170373091A1

公开(公告)日：2017-12-28

申请号：US15436066

申请日：2017-02-17

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： JI HUN LIM ,  Joon Seok Park

IPC分类号： H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L27/124 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78669 ,  H01L29/7869

摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.

公开(公告)号：US20190139992A1

公开(公告)日：2019-05-09

申请号：US16241247

申请日：2019-01-07

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： JI HUN LIM ,  Joon Seok Park

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L27/124 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78696

摘要： A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.