Display device having electrostatic protection circuit

    公开(公告)号:US12279490B2

    公开(公告)日:2025-04-15

    申请号:US17465795

    申请日:2021-09-02

    Abstract: A display device including a substrate; a signal line disposed on the substrate and to which a predetermined voltage signal is applied; a power auxiliary line to which a first source voltage is applied; a first driving voltage line to which a first driving voltage higher than the first source voltage is applied; and a first transistor disposed between the signal line and the first driving voltage line. The first transistor includes a first lower gate electrode connected to the power auxiliary line and a first upper gate electrode connected to the signal line.

    DISPLAY DEVICE
    5.
    发明申请

    公开(公告)号:US20220157915A1

    公开(公告)日:2022-05-19

    申请号:US17465795

    申请日:2021-09-02

    Abstract: A display device including a substrate; a signal line disposed on the substrate and to which a predetermined voltage signal is applied; a power auxiliary line to which a first source voltage is applied; a first driving voltage line to which a first driving voltage higher than the first source voltage is applied; and a first transistor disposed between the signal line and the first driving voltage line. The first transistor includes a first lower gate electrode connected to the power auxiliary line and a first upper gate electrode connected to the signal line.

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号:US20160035750A1

    公开(公告)日:2016-02-04

    申请号:US14596780

    申请日:2015-01-14

    Abstract: A thin film transistor array panel is provided. A thin film transistor is positioned on a substrate. A first passivation layer is positioned on the thin film transistor. A common electrode is positioned on the first passivation layer. A second passivation layer positioned on the common electrode. A pixel electrode is positioned on the second passivation layer. The pixel electrode is coupled to the thin film transistor through a first contact hole penetrating the first passivation layer, the common electrode, and the second passivation layer. A first part of the first contact hole formed in the common electrode is larger than a second part of the first contact hole formed in the second passivation layer.

    Abstract translation: 提供薄膜晶体管阵列面板。 薄膜晶体管位于基板上。 第一钝化层位于薄膜晶体管上。 公共电极位于第一钝化层上。 位于公共电极上的第二钝化层。 像素电极位于第二钝化层上。 像素电极通过穿过第一钝化层,公共电极和第二钝化层的第一接触孔耦合到薄膜晶体管。 形成在公共电极中的第一接触孔的第一部分大于形成在第二钝化层中的第一接触孔的第二部分。

    DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20220336669A1

    公开(公告)日:2022-10-20

    申请号:US17646973

    申请日:2022-01-04

    Abstract: A display device according to an embodiment includes: a substrate; a first conductive layer positioned on the substrate; a semiconductor layer positioned on the first conductive layer; a second conductive layer positioned on the semiconductor layer; an oxygen supply layer positioned under the second conductive layer, in contact with the second conductive layer, and having the same planar shape as the second conductive layer; and a light-emitting element connected to the second conductive layer, wherein the oxygen supply layer includes a metal oxide that includes one or more of indium, zinc, tin, or gallium, or alloys thereof.

    Liquid crystal display
    9.
    发明授权

    公开(公告)号:US11422421B2

    公开(公告)日:2022-08-23

    申请号:US16785554

    申请日:2020-02-07

    Abstract: A liquid crystal display includes a gate line; a data line crossing the gate line; a first voltage line spaced apart from the gate line; a second voltage line, a first transistor including a first gate electrode connected to the gate line, a first source electrode connected to the data line, and a first drain electrode; a second transistor including a second gate electrode connected to the gate line, a second source electrode connected to the data line, and a second drain electrode; a third transistor including a third gate electrode connected to the first voltage line, a third source electrode connected to the second drain electrode, and a third drain electrode connected to the second voltage line; a first liquid crystal capacitor connected to the first drain electrode of the first transistor; and a second liquid crystal capacitor connected to the second drain electrode of the second transistor.

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