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公开(公告)号：US09721494B2
公开(公告)日：2017-08-01
申请号：US15141583
申请日：2016-04-28
发明人： Jae-Han Lee , Taegon Kim , Young-Il Ban , Sunkyu Son
CPC分类号： G09G3/2003 , G09G3/20 , G09G5/18 , G09G2300/0408 , G09G2310/0286 , G09G2310/0291 , G09G2320/0242 , G09G2320/0276 , G09G2320/0646 , G09G2330/028 , G09G2370/08
摘要： A controller for a display panel includes a detector, a timing controller, and a voltage generator. The detector detects a predetermined pattern in an image signal. The timing controller generates a control signal based on detection of the pattern. The voltage generator changes at least one driving voltage for a display panel from a first level to a second level based on the control signal. The predetermined pattern may correspond to at least one region having a predetermined arrangement of at least first and second gray scale values of pixels in an image corresponding to the image signal.
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2.发明授权Method of driving a display panel, display panel driving apparatus for performing the method and display apparatus having the display panel driving apparatus 有权驱动显示面板的方法，用于执行该方法的显示面板驱动装置和具有该显示面板驱动装置的显示装置公开(公告)号：US09530373B2
公开(公告)日：2016-12-27
申请号：US14286769
申请日：2014-05-23
发明人： Young-Il Ban , Sun-Koo Kang , Seung-Hwan Moon , Sun-Kyu Son , Kyung-Ha Kim , Jae-Han Lee
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0248 , G09G2330/023 , G09G2360/16 , G09G2370/08
摘要： A display panel driving apparatus includes an image pattern analyzing part, a clock signal generating part and a data driving part. The image pattern analyzing part is configured to analyze an image pattern of an image data. The clock signal generating part is configured to generating a clock signal having a different pulse width according to the image pattern of an image data. The data driving part is configured to drive a data line of a display panel in response to the clock signal. Thus, power consumption and heating of the data driving part may be decreased.
摘要翻译： 显示面板驱动装置包括图像图案分析部，时钟信号生成部和数据驱动部。 图像图案分析部被配置为分析图像数据的图像图案。 时钟信号生成部被配置为根据图像数据的图像图像生成具有不同脉冲宽度的时钟信号。 数据驱动部件被配置为响应于时钟信号来驱动显示面板的数据线。 因此，可以降低数据驱动部的功耗和加热。
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公开(公告)号：US09646561B2
公开(公告)日：2017-05-09
申请号：US14818352
申请日：2015-08-05
发明人： Jae-Han Lee , Sun-Koo Kang , Sooyeon Kim , Young-Il Ban
CPC分类号： G09G3/3688 , G09G3/006 , G09G2300/0426 , G09G2310/027
摘要： A display device includes a display panel, a gate driver, a data driver, and a driving control unit. The display panel includes pixels connected to a corresponding one of gate lines and a corresponding one of data lines. The gate driver drives the gate lines. The data driver includes first pads and second pads. The first pads are connected to each of first data lines of the data lines, and the second pads are connected to each of second data lines of the data lines. The driving control unit provides control signals and a data signal to the data driver, and to control the gate driver. The data driver includes a digital-to-analog converter and a switching circuit. The digital-to-analog converter converts the data signal into analog signals. The switching circuit sequentially outputs the analog signals to the first pads during a test mode.
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公开(公告)号：US09251755B2
公开(公告)日：2016-02-02
申请号：US14470511
申请日：2014-08-27
发明人： Ok-Kwon Shin , Jong Min Lee , Sun Kyu Son , Young-Il Ban , Jae-Han Lee
CPC分类号： G09G3/3674 , G09G3/3677 , G09G2310/0205 , G09G2310/0286 , G09G2310/08 , G11C19/28 , G11C19/287
摘要： A gate driver includes a gate integrated circuit (“IC”) chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, where at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, timings of the at least two scanning start signals are independent of each other, and timings of the at least two clock control signals based on the one scanning start signal are independent of each other.
摘要翻译： 栅极驱动器包括：门集成电路（IC）芯片，其接收至少两个扫描开始信号和至少四个时钟控制信号，并且输出多个栅极导通电压，其中至少两个时钟控制信号 基于所述至少两个扫描开始信号的一个扫描开始信号生成至少四个时钟控制信号，所述至少两个扫描开始信号的定时彼此独立，并且所述至少两个时钟控制信号的定时基于 一个扫描开始信号彼此独立。
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公开(公告)号：US20200184918A1
公开(公告)日：2020-06-11
申请号：US16794787
申请日：2020-02-19
发明人： WONTAE KIM , Sooyeon Kim , Young-Il Ban , Sunkyu Son
IPC分类号： G09G3/36
摘要： Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals
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公开(公告)号：US10249226B2
公开(公告)日：2019-04-02
申请号：US15146952
申请日：2016-05-05
发明人： Sooyeon Kim , Wontae Kim , Young-Il Ban , Sunkyu Son
IPC分类号： G09G3/20
摘要： A driving method of a display device includes sequentially outputting a plurality of eye tuning signals, receiving a plurality of checking information obtained from a data driving circuit, wherein the checking information indicates whether the data driving circuit is operating in response to each of the plurality of eye tuning signals, and selecting one optimal eye tuning signal among the plurality of eye tuning signals operating the data driving circuit on the basis of the checking information. Image signals are output on the basis of condition information of the optimal eye tuning signal.
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7.发明授权公开(公告)号：US09984643B2
公开(公告)日：2018-05-29
申请号：US15145172
申请日：2016-05-03
发明人： Young-Il Ban , Sun-Koo Kang , Tae-Gon Kim
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3607 , G09G2300/0452 , G09G2310/027 , G09G2320/0673
摘要： A data driver includes a first data voltage generator, a data converter and a second data voltage generator. The first data voltage generator is configured to generate a first data voltage based on first pixel data and configured to output the first data voltage to a first data line, the first pixel data being generated based on a first gamma curve. The data converter is configured to convert second pixel data to first converted pixel data, the second pixel data being generated based on the first gamma curve, the first converted pixel data being generated based on a second gamma curve different from the first gamma curve. The second data voltage generator is configured to generate a second data voltage based on the first converted pixel data and configured to output the second data voltage to a second data line.
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公开(公告)号：US20230075010A1
公开(公告)日：2023-03-09
申请号：US18050080
申请日：2022-10-27
发明人： WONTAE KIM , Sooyeon Kim , Young-Il Ban , Sunkyu Son
IPC分类号： G09G3/36
摘要： Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals
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公开(公告)号：US11488560B2
公开(公告)日：2022-11-01
申请号：US16794787
申请日：2020-02-19
发明人： Wontae Kim , Sooyeon Kim , Young-Il Ban , Sunkyu Son
IPC分类号： G09G3/36
摘要： Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.
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10.发明授权公开(公告)号：US09734752B2
公开(公告)日：2017-08-15
申请号：US14751944
申请日：2015-06-26
发明人： Jae-Han Lee , Sooyeon Kim , Young-Il Ban , Sunkyu Son
IPC分类号： G09G3/20 , G09G3/00 , G02F1/1345
CPC分类号： G09G3/2096 , G02F1/13452 , G09G3/006 , G09G3/20 , G09G2300/0413 , G09G2310/0275 , G09G2310/061 , G09G2310/08 , G09G2330/021 , G09G2330/12
摘要： A display device including: a display panel displaying an image based on first and second frames; a timing controller outputting a plurality of image signals for each of the first and second frames and outputting a test signal during a reset section; and a source driving chip outputting a plurality of data voltages corresponding to the image signals or a test voltage corresponding to the test signal. The reset section is arranged after the first frame and before the second frame, and the source driving chip blocks the data voltage in the second frame from being output to driving lines having an arrival time period equal to or less than a reference time period during the reset section, the arrival time period representing the amount of time taken to arrive at the test voltage from an initial voltage.
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