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公开(公告)号：US11514832B2
公开(公告)日：2022-11-29
申请号：US17374893
申请日：2021-07-13
发明人： Sooyeon Kim , Taegon Im , Jihyun Kim , Jiye Lee
IPC分类号： G09G3/20
摘要： A display apparatus includes a display panel, a gamma reference voltage generator and a data driver. The gamma reference voltage generator is configured to generate a gamma reference voltage. The gamma reference voltage includes a gamma amplifier configured to output the gamma reference voltage. The data driver is configured to generate a data voltage based on the gamma reference voltage and to output the data voltage to the display panel. A polarity of an offset voltage of the gamma amplifier is inverted alternately in a unit of one frame and in a unit of two frames.
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公开(公告)号：US09646561B2
公开(公告)日：2017-05-09
申请号：US14818352
申请日：2015-08-05
发明人： Jae-Han Lee , Sun-Koo Kang , Sooyeon Kim , Young-Il Ban
CPC分类号： G09G3/3688 , G09G3/006 , G09G2300/0426 , G09G2310/027
摘要： A display device includes a display panel, a gate driver, a data driver, and a driving control unit. The display panel includes pixels connected to a corresponding one of gate lines and a corresponding one of data lines. The gate driver drives the gate lines. The data driver includes first pads and second pads. The first pads are connected to each of first data lines of the data lines, and the second pads are connected to each of second data lines of the data lines. The driving control unit provides control signals and a data signal to the data driver, and to control the gate driver. The data driver includes a digital-to-analog converter and a switching circuit. The digital-to-analog converter converts the data signal into analog signals. The switching circuit sequentially outputs the analog signals to the first pads during a test mode.
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公开(公告)号：US20230075010A1
公开(公告)日：2023-03-09
申请号：US18050080
申请日：2022-10-27
发明人： WONTAE KIM , Sooyeon Kim , Young-Il Ban , Sunkyu Son
IPC分类号： G09G3/36
摘要： Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals
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公开(公告)号：US11488560B2
公开(公告)日：2022-11-01
申请号：US16794787
申请日：2020-02-19
发明人： Wontae Kim , Sooyeon Kim , Young-Il Ban , Sunkyu Son
IPC分类号： G09G3/36
摘要： Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.
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5.发明授权公开(公告)号：US09734752B2
公开(公告)日：2017-08-15
申请号：US14751944
申请日：2015-06-26
发明人： Jae-Han Lee , Sooyeon Kim , Young-Il Ban , Sunkyu Son
IPC分类号： G09G3/20 , G09G3/00 , G02F1/1345
CPC分类号： G09G3/2096 , G02F1/13452 , G09G3/006 , G09G3/20 , G09G2300/0413 , G09G2310/0275 , G09G2310/061 , G09G2310/08 , G09G2330/021 , G09G2330/12
摘要： A display device including: a display panel displaying an image based on first and second frames; a timing controller outputting a plurality of image signals for each of the first and second frames and outputting a test signal during a reset section; and a source driving chip outputting a plurality of data voltages corresponding to the image signals or a test voltage corresponding to the test signal. The reset section is arranged after the first frame and before the second frame, and the source driving chip blocks the data voltage in the second frame from being output to driving lines having an arrival time period equal to or less than a reference time period during the reset section, the arrival time period representing the amount of time taken to arrive at the test voltage from an initial voltage.
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公开(公告)号：US12027094B2
公开(公告)日：2024-07-02
申请号：US17115838
申请日：2020-12-09
发明人： Sooyeon Kim , Hee-Jeong Seo , Jiye Lee , Taegon Im , Junghwan Cho
IPC分类号： G09G3/3275 , G09G3/20
CPC分类号： G09G3/2092 , G09G2310/027 , G09G2310/0275
摘要： Provided is a data driver including a digital to analog converter configured to convert image signal data into a plurality of data voltages, and an output buffer unit including a plurality of channels for outputting the plurality of data voltages. The output buffer unit includes a plurality of output blocks. Each output block includes one or more channels. Data voltages outputted from a first output block among the plurality of output blocks are delayed with a first time difference. Data voltages outputted from a second output block among the plurality of output blocks are delayed with a second time difference which is different from the first time difference.
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公开(公告)号：US10909897B2
公开(公告)日：2021-02-02
申请号：US16556080
申请日：2019-08-29
发明人： Jae-Han Lee , Sooyeon Kim , Taegon Im , Jung Hwan Cho
摘要： A gate driving circuit includes a shift register configured to generate a plurality of output signals based on at least one clock signal, a plurality of output buffers configured to generate a plurality of gate signals by amplifying the output signals and to sequentially output the gate signals to a plurality of gate lines in a display panel, a detector configured to sequentially sense the gate signals and to compare each of the gate signals to a reference voltage, and a dummy output buffer configured to be coupled between the shift register and a gate line of the gate lines instead of an output buffer of the output buffers when a voltage level of a corresponding gate signal from the output buffers is less than a voltage level of the reference voltage.
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公开(公告)号：US20200184918A1
公开(公告)日：2020-06-11
申请号：US16794787
申请日：2020-02-19
发明人： WONTAE KIM , Sooyeon Kim , Young-Il Ban , Sunkyu Son
IPC分类号： G09G3/36
摘要： Provided is a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals
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公开(公告)号：US10249226B2
公开(公告)日：2019-04-02
申请号：US15146952
申请日：2016-05-05
发明人： Sooyeon Kim , Wontae Kim , Young-Il Ban , Sunkyu Son
IPC分类号： G09G3/20
摘要： A driving method of a display device includes sequentially outputting a plurality of eye tuning signals, receiving a plurality of checking information obtained from a data driving circuit, wherein the checking information indicates whether the data driving circuit is operating in response to each of the plurality of eye tuning signals, and selecting one optimal eye tuning signal among the plurality of eye tuning signals operating the data driving circuit on the basis of the checking information. Image signals are output on the basis of condition information of the optimal eye tuning signal.
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公开(公告)号：US20160125792A1
公开(公告)日：2016-05-05
申请号：US14751944
申请日：2015-06-26
发明人： Jae-Han LEE , Sooyeon Kim , Young-II Ban , Sunkyu Son
CPC分类号： G09G3/2096 , G02F1/13452 , G09G3/006 , G09G3/20 , G09G2300/0413 , G09G2310/0275 , G09G2310/061 , G09G2310/08 , G09G2330/021 , G09G2330/12
摘要： A display device including: a display panel displaying an image based on first and second frames; a timing controller outputting a plurality of image signals for each of the first and second frames and outputting a test signal during a reset section; and a source driving chip outputting a plurality of data voltages corresponding to the image signals or a test voltage corresponding to the test signal. The reset section is arranged after the first frame and before the second frame, and the source driving chip blocks the data voltage in the second frame from being output to driving lines having an arrival time period equal to or less than a reference time period during the reset section, the arrival time period representing the amount of time taken to arrive at the test voltage from an initial voltage.
摘要翻译： 一种显示装置，包括：基于第一和第二帧显示图像的显示面板; 定时控制器，为第一和第二帧中的每一个输出多个图像信号，并在复位部分期间输出测试信号; 以及源极驱动芯片，其输出对应于图像信号的多个数据电压或对应于测试信号的测试电压。 复位部分布置在第一帧之后和第二帧之前，并且源驱动芯片阻止第二帧中的数据电压被输出到具有等于或小于参考时间段的到达时间段的驱动线 复位部分，表示从初始电压到达测试电压所花费的时间量的到达时间段。
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