公开(公告)号：US20220164164A1

公开(公告)日：2022-05-26

申请号：US17356771

申请日：2021-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Dal KWON ,  Ho Young KIM ,  Hanmin PARK ,  Jaehyeong SIM ,  Seung Wook LEE ,  Jae-Eon JO

IPC: G06F7/50 ,  G06N3/08 ,  G06F7/544

Abstract: An apparatus with deep learning includes: a systolic adder tree including adder trees connected in row and column directions; and an input multiplexer connected to an input register of at least one of the adder trees and configured to determine column directional data movement between the adder trees based on operation modes.

公开(公告)号：US20220083390A1

公开(公告)日：2022-03-17

申请号：US17223139

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jae-Eon JO ,  Hyung-Dal KWON ,  Hanmin PARK ,  Jaehyeong SIM ,  Seung Wook LEE

IPC: G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06F9/48 ,  G06F1/3237

Abstract: A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.

公开(公告)号：US20220035629A1

公开(公告)日：2022-02-03

申请号：US17102884

申请日：2020-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Dal KWON ,  Hanmin PARK ,  Seungwook LEE ,  Jae-Eon JO

IPC: G06F9/30 ,  G06F7/57 ,  G06F7/533 ,  G06F17/14 ,  G06N3/08

Abstract: Disclosed is an apparatus and method for performing deep learning operations. The apparatus includes a systolic array comprising multiplier accumulator (MAC) units, and a control circuit configured to control an operation of a multiplexer connected to at least one of the MAC units and operations of the MAC units according to a plurality of operation modes.

公开(公告)号：US20240411562A1

公开(公告)日：2024-12-12

申请号：US18461766

申请日：2023-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Eon JO ,  Rohyoung MYUNG

IPC: G06F9/38 ,  G06F9/50

Abstract: A process-implemented method includes: based on obtaining a job description on an application, determining a wall clock time of the application according to processes of a corresponding candidate count for each of a plurality of candidate counts; determining parallelization efficiency for each of the candidate counts based on the determined wall clock time and a wall clock time of the application according to a single process; and executing the application with processes of a target count selected based on the determined parallelization efficiency among the plurality of candidate counts.

公开(公告)号：US20240004809A1

公开(公告)日：2024-01-04

申请号：US18364872

申请日：2023-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanmin PARK ,  Hyung-Dal KWON ,  Jaehyeong SIM ,  Seungwook LEE ,  Jae-Eon JO

IPC: G06F13/16 ,  G06N3/04

CPC classification number: G06F13/1668 ,  G06N3/04

Abstract: An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.

公开(公告)号：US20220066960A1

公开(公告)日：2022-03-03

申请号：US17182439

申请日：2021-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanmin PARK ,  Hyung-Dal KWON ,  Jaehyeong SIM ,  Seungwook LEE ,  Jae-Eon JO

IPC: G06F13/16 ,  G06N3/04

Abstract: An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.