公开(公告)号：US20210035895A1

公开(公告)日：2021-02-04

申请号：US16835915

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUHYEON OH ,  WOOJIN CHOI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package may include a substrate having an upper surface on which a plurality of first pads are disposed and a lower surface on which a plurality of second pads are disposed. The semiconductor package may further include a semiconductor chip disposed on the upper surface of the substrate on which connection electrodes connected to a first set of the plurality of first pads are disposed. The semiconductor package may include an interposer having an upper surface on which a plurality of first connection pads, connected to a second set of the plurality of first pads, and a plurality of second connection pads are disposed. The semiconductor package may further include a plurality of connection terminals disposed on a set of the plurality of second connection pads of the interposer, and a molding material disposed on the upper surface of the substrate.

公开(公告)号：US20240347401A1

公开(公告)日：2024-10-17

申请号：US18754605

申请日：2024-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYONG HWAN KOH ,  JONGWAN KIM ,  JUHYEON OH ,  YONGKWAN LEE

IPC: H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/13 ,  H01L21/4803 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/06135 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/73265

Abstract: A semiconductor package includes a base substrate that includes a first surface and a second surface that face each other, a plurality of first metal line patterns disposed on the first surface, a plurality of second metal line patterns disposed on the second surface, a plurality of vias that penetrate the base substrate and connect the first metal line patterns to the second metal line patterns, a semiconductor chip disposed on the first surface, and a molding member that covers the first surface and the semiconductor chip. The base substrate includes at least one recess at a corner of the base substrate. The recess extends from the first surface toward the second surface. The molding member includes a protrusion that fills the recess.

公开(公告)号：US20250062304A1

公开(公告)日：2025-02-20

申请号：US18749275

申请日：2024-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： SEOKGEUN AHN ,  JUHYEON OH ,  DAEHO LEE ,  MINHYUK JUNG ,  EUNHEE JUNG

IPC: H01L25/18 ,  G02B6/42 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

Abstract: A semiconductor package includes a package substrate, a semiconductor chip disposed on an upper surface of the package substrate, and an EIC chip disposed on the package substrate and spaced apart from the semiconductor chip in a horizontal direction parallel to the upper surface of the package substrate. The semiconductor package further includes a PIC chip disposed on an upper surface of the EIC chip, wherein a horizontal surface area of the PIC chip is greater than a horizontal surface area of the EIC chip, and wherein a portion of PIC chip protrudes horizontally from the EIC chip. The semiconductor package further includes a reflective portion disposed on a lower surface of the portion of the PIC chip and spaced apart from the EIC chip in the horizontal direction, and an optical fiber connected to the reflective portion and spaced apart from the PIC chip in a vertical direction.

公开(公告)号：US20200043854A1

公开(公告)日：2020-02-06

申请号：US16424000

申请日：2019-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUHYEON OH ,  SUNCHUL KIM ,  HYUNKI KIM

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.