公开(公告)号：US20230114892A1

公开(公告)日：2023-04-13

申请号：US17745601

申请日：2022-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGWAN KIM ,  YONGKWAN LEE ,  KYONGHWAN KOH ,  SEUNGHWAN KIM ,  JUNGJOO KIM ,  JUNWOO PARK ,  TAEJUN JEON

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L23/29

Abstract: A semiconductor package includes; a package substrate, a semiconductor chip on the package substrate, an electromagnetic shield structure on the package substrate and including an upper cover covering an upper surface of the semiconductor chip and a side cover surrounding the semiconductor chip, and a sealing member contacting the semiconductor chip and the electromagnetic shield structure, wherein the side cover includes first through holes and the upper cover includes second through holes.

公开(公告)号：US20250079232A1

公开(公告)日：2025-03-06

申请号：US18596869

申请日：2024-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEJAE PARK ,  YONGKWAN LEE ,  SUNCHUL KIM ,  JUNGSOO JEON

IPC: H01L21/687 ,  H01L21/48 ,  H01L21/67 ,  H01L21/683

Abstract: A semiconductor package bonding tool includes a bonding plate and bonding blocks disposed on a bottom surface of the bonding plate. The bonding plate include first vacuum holes that vertically penetrate the bonding plate. The first vacuum holes connect a top surface of the bonding plate to the bottom surface of the bonding plate. Each of the bonding blocks includes a bonding stage disposed below a respective first vacuum hole of the first vacuum holes. The bonding stage includes a trench hole upwardly recessed from a bottom surface of the bonding stage, and a connection hole connecting a top surface of the bonding stage to the trench hole. A length in a horizontal direction of the trench hole is greater than that of the connection hole.

公开(公告)号：US20240347401A1

公开(公告)日：2024-10-17

申请号：US18754605

申请日：2024-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYONG HWAN KOH ,  JONGWAN KIM ,  JUHYEON OH ,  YONGKWAN LEE

IPC: H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/13 ,  H01L21/4803 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/06135 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/73265

Abstract: A semiconductor package includes a base substrate that includes a first surface and a second surface that face each other, a plurality of first metal line patterns disposed on the first surface, a plurality of second metal line patterns disposed on the second surface, a plurality of vias that penetrate the base substrate and connect the first metal line patterns to the second metal line patterns, a semiconductor chip disposed on the first surface, and a molding member that covers the first surface and the semiconductor chip. The base substrate includes at least one recess at a corner of the base substrate. The recess extends from the first surface toward the second surface. The molding member includes a protrusion that fills the recess.

公开(公告)号：US20220415778A1

公开(公告)日：2022-12-29

申请号：US17655573

申请日：2022-03-21

Applicant: Samsung Electronics Co., LTD.

Inventor： JUNWOO PARK ,  SEUNGHWAN KIM ,  JUNGJOO KIM ,  YONGKWAN LEE ,  DONGJU JANG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a lower substrate that includes a lower wiring layer; a semiconductor chip disposed on the lower substrate, and an upper substrate disposed on the semiconductor chip. The upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface. The lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate. The cavity region and the plurality of channel regions are defined by the plurality of protruding structures.