公开(公告)号：US20190393205A1

公开(公告)日：2019-12-26

申请号：US16250000

申请日：2019-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Seong LEE ,  Ah-Reum KIM ,  Min-Su KIM ,  Jong-Kyu RYU

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092 ,  H01L23/50

Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

公开(公告)号：US20190173472A1

公开(公告)日：2019-06-06

申请号：US16259631

申请日：2019-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah-Reum KIM ,  Hyun LEE ,  Min-su KIM

IPC: H03K19/0185 ,  H03K3/356 ,  H03K3/037 ,  H03K19/00 ,  H03K3/012

CPC classification number: H03K19/01855 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356191 ,  H03K19/0013

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

公开(公告)号：US20160315616A1

公开(公告)日：2016-10-27

申请号：US15139949

申请日：2016-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah-Reum KIM ,  Hyun LEE ,  Min-Su KIM

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/01855 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356191 ,  H03K19/0013

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

Abstract translation: 提供半导体电路。 半导体电路包括：第一电路，被配置为基于时钟信号的电压电平将第一节点的值传播到第二节点; 第二电路，被配置为基于所述时钟信号的电压电平将所述第二节点的值传播到第三节点; 以及第三电路，被配置为基于所述第二节点的电压电平和所述时钟信号的电压电平来确定所述第三节点的值，其中所述第一电路包括门控到所述第一节点的电压电平的第一晶体管， 第二晶体管，其与第一晶体管串联连接，并与第三晶体管的电压电平相连，第三晶体管与第一和第二晶体管并联连接，并且选通到时钟信号的电压电平，以提供第一晶体管的值 节点到第二个节点。