公开(公告)号：US20170207234A1

公开(公告)日：2017-07-20

申请号：US15476044

申请日：2017-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNMOG PARK ,  DAEWOONG KANG ,  CHADONG YEO ,  JAEHOON JANG ,  JOONGSHIK SHIN

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L29/16 ,  H01L27/11529 ,  H01L27/11556 ,  H01L29/04 ,  H01L27/1157 ,  H01L27/11524

CPC classification number: H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/16 ,  H01L29/4966

Abstract: A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.