公开(公告)号：US20170207234A1

公开(公告)日：2017-07-20

申请号：US15476044

申请日：2017-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNMOG PARK ,  DAEWOONG KANG ,  CHADONG YEO ,  JAEHOON JANG ,  JOONGSHIK SHIN

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L29/16 ,  H01L27/11529 ,  H01L27/11556 ,  H01L29/04 ,  H01L27/1157 ,  H01L27/11524

CPC classification number: H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/045 ,  H01L29/16 ,  H01L29/4966

Abstract: A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.

公开(公告)号：US20160049346A1

公开(公告)日：2016-02-18

申请号：US14925789

申请日：2015-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-JOO SHIM ,  HANSOO KIM ,  WONSEOK CHO ,  JAEHOON JANG ,  WOOJIN CHO

IPC: H01L23/31 ,  H01L23/29 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract translation: 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括布置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。