公开(公告)号：US20210374001A1

公开(公告)日：2021-12-02

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINSU KIM ,  NAM HYUNG KIM ,  DAE-JEONG KIM ,  DO-HAN KIM ,  DEOKHO SEO ,  WONJAE SHIN ,  YONGJUN YU ,  CHANGMIN LEE ,  INSU CHOI

IPC: G06F11/10 ,  G11C11/408 ,  G11C11/4091

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

公开(公告)号：US20250006242A1

公开(公告)日：2025-01-02

申请号：US18522252

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGHA KIM ,  DO-HAN KIM ,  BOBAE KIM ,  CHANGMIN LEE ,  KYEONGJIN CHO

IPC: G11C11/406

Abstract: A memory device according to an embodiment includes a memory cell array including a plurality of memory cells disposed in a plurality of rows, a register configured to store row addresses corresponding to the plurality of rows and access counts for the plurality of rows, and a refresh controller configured to determine a refresh address based on the stored row addresses and a refresh command being received, and change a refresh period for a target row based on the refresh address being associated with a previously performed refresh for the target row and the access count for a row corresponding to the target row being reached a threshold value.

公开(公告)号：US20230350809A1

公开(公告)日：2023-11-02

申请号：US18140974

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHINAM KIM ,  TAEKYEONG KO ,  NAMHYUNG KIM ,  DOHAN KIM ,  BYEONGNOH KIM ,  BOBAE KIM ,  CHANGMIN LEE ,  KYEONGJIN CHO ,  INSU CHOI

IPC: G06F12/10

CPC classification number: G06F12/10

Abstract: A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

公开(公告)号：US20250044941A1

公开(公告)日：2025-02-06

申请号：US18441475

申请日：2024-02-14

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： CHINAM KIM ,  DO-HAN KIM ,  CHANGMIN LEE

IPC: G06F3/06

Abstract: A memory device with a computation function includes a first cell array including first memory cells connected to word lines, a second cell array including second memory cells connected to the word lines, a first bit line sense amplifier that sense first voltages of first bit lines connected to the first memory cells, a second bit line sense amplifier that senses second voltages of second bit lines connected to the second memory cells, a first column selection circuit that outputs a first output signal among the first voltages based on a first column compute selection signal, a second column selection circuit that outputs a second output signal among the second voltages based on a second column compute selection signal different from the first column compute selection signal, and a column compute control circuit that generates the first column compute selection signal and the second column compute selection signal.

公开(公告)号：US20210373995A1

公开(公告)日：2021-12-02

申请号：US17105821

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONJAE SHIN ,  NAM HYUNG KIM ,  DAE-JEONG KIM ,  DO-HAN KIM ,  MINSU KIM ,  DEOKHO SEO ,  YONGJUN YU ,  CHANGMIN LEE ,  INSU CHOI

IPC: G06F11/10 ,  G06F11/30 ,  G06F11/16

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.