公开(公告)号：US20210374001A1

公开(公告)日：2021-12-02

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINSU KIM ,  NAM HYUNG KIM ,  DAE-JEONG KIM ,  DO-HAN KIM ,  DEOKHO SEO ,  WONJAE SHIN ,  YONGJUN YU ,  CHANGMIN LEE ,  INSU CHOI

IPC: G06F11/10 ,  G11C11/408 ,  G11C11/4091

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

公开(公告)号：US20210373995A1

公开(公告)日：2021-12-02

申请号：US17105821

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONJAE SHIN ,  NAM HYUNG KIM ,  DAE-JEONG KIM ,  DO-HAN KIM ,  MINSU KIM ,  DEOKHO SEO ,  YONGJUN YU ,  CHANGMIN LEE ,  INSU CHOI

IPC: G06F11/10 ,  G06F11/30 ,  G06F11/16

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.