中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.054 seconds)

    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240080027A1

    公开(公告)日：2024-03-07

    申请号：US18241555

    申请日：2023-09-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： MINSU KIM

    IPC: H03K19/00 ,  H01L27/02 ,  H03K3/356 ,  H03K19/0185

    CPC classification number: H03K19/0016 ,  H01L27/0207 ,  H03K3/356121 ,  H03K19/018521

    Abstract: A semiconductor device includes: a first layer including a first semiconductor substrate, a plurality of first standard cell regions defined in the first semiconductor substrate, and a plurality of first standard cells disposed in the plurality of first standard cell regions; and a second layer including a second semiconductor substrate, a plurality of second standard cell regions defined in the second semiconductor substrate, and a plurality of second standard cells disposed in the plurality of second standard cell regions, the second layer being stacked with the first layer in a vertical direction perpendicular to an upper surface of the first semiconductor substrate, wherein the plurality of first standard cells provide combinational logic circuits, and the plurality of second standard cells provide at least some of sequential logic circuits, a clock gate circuit, a power circuit, and a level shifter circuit.

    HYBRID STANDARD CELL AND METHOD OF DESIGNING INTEGRATED CIRCUIT USING THE SAME
    2.
    发明申请
    HYBRID STANDARD CELL AND METHOD OF DESIGNING INTEGRATED CIRCUIT USING THE SAME 有权

    公开(公告)号：US20210143800A1

    公开(公告)日：2021-05-13

    申请号：US16891521

    申请日：2020-06-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JEONGJIN LEE ,  MINSU KIM ,  AHREUM KIM

    IPC: H03K3/012 ,  H03K3/3562 ,  H01L27/092 ,  G06F30/3953 ,  G06F30/398 ,  G06F30/392

    Abstract: The present disclosure relates to a hybrid standard cell that includes a semiconductor substrate, a first power rail, a second power rail, a high-speed transistor region and a low-power transistor region. The first power rail and the second power rail are formed above the semiconductor substrate and extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The high-speed transistor region and the low-power transistor region are adjacent to each other in the first direction and arranged in a row region between the first power rail and the second power rail. An operation speed of a high-speed transistor formed in the high-speed transistor region is higher than an operation speed of a low-power transistor formed in the low-power transistor region, and a power consumption of the high-speed transistor is lower than a power consumption of the high-speed transistor.

    CLOCK GATING CIRCUIT OPERATES AT HIGH SPEED
    3.
    发明申请
    CLOCK GATING CIRCUIT OPERATES AT HIGH SPEED 审中-公开

    公开(公告)号：US20180287612A1

    公开(公告)日：2018-10-04

    申请号：US16001701

    申请日：2018-06-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYUNCHUL HWANG ,  MINSU KIM

    IPC: H03K19/00

    CPC classification number: H03K19/0016 ,  G06F1/3237 ,  H03K19/0013 ,  Y02D10/128

    Abstract: A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

    CLOCK GATING CIRCUIT OPERATES AT HIGH SPEED
    5.
    发明申请
    CLOCK GATING CIRCUIT OPERATES AT HIGH SPEED 审中-公开

    公开(公告)号：US20170324410A1

    公开(公告)日：2017-11-09

    申请号：US15660527

    申请日：2017-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYUNCHUL HWANG ,  MINSU KIM

    IPC: H03K19/00

    CPC classification number: H03K19/0016 ,  G06F1/3237 ,  H03K19/0013

    Abstract: A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

    MULTI-BIT FLIP-FLOP CIRCUIT WITH REDUCED AREA AND REDUCED WIRE COMPLEXITY
    7.
    发明公开
    MULTI-BIT FLIP-FLOP CIRCUIT WITH REDUCED AREA AND REDUCED WIRE COMPLEXITY 审中-公开

    公开(公告)号：US20230318584A1

    公开(公告)日：2023-10-05

    申请号：US18092507

    申请日：2023-01-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： WONHYUN CHOI ,  HYUNCHUL HWANG ,  MINSU KIM

    IPC: H03K3/037

    CPC classification number: H03K3/037

    Abstract: A multi-bit flip-flop includes a first bit flip-flop and a second bit flip-flop. The first bit flip-flop includes an input multiplexer that receives a first and second data bits, and outputs one of the first and second data bits as a third data bit; a first transmission circuit; a first latch; a second transmission circuit; and a second latch that outputs a first output data bit. The second bit flip-flop includes an input multiplexer that receives a fourth data bit and the first output data bit, and outputs one of the fourth data bit and the first output data bit as a fifth data bit; a first transmission circuit, a first latch, a second transmission circuit, and a second latch that outputs a second output data bit. The first output data bit is provided from the first bit flip-flop to the second bit flip-flop along an external wire.

    CLOCK GATING CIRCUIT THAT OPERATES AT HIGH SPEED
    9.
    发明申请
    CLOCK GATING CIRCUIT THAT OPERATES AT HIGH SPEED 有权
    高速运行的时钟增益电路

    公开(公告)号：US20160373112A1

    公开(公告)日：2016-12-22

    申请号：US15153799

    申请日：2016-05-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYUNCHUL HWANG ,  MINSU KIM

    IPC: H03K19/00

    CPC classification number: H03K19/0016 ,  G06F1/3237 ,  H03K19/0013

    Abstract: A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

    Abstract translation: 时钟选通电路包括基于时钟信号对第一节点充电的第一预充电单元，基于时钟信号对第二节点充电的第二预充电单元，基于时钟信号对第一节点放电的第一放电单元，第二放电 基于所述时钟信号对所述第二节点进行放电;第一交叉耦合维持单元，根据所述第二节点的电压电平将所述第一节点保持在充电状态;第二交叉耦合维持单元，将所述第二节点维持在充电状态 根据第一节点的电压电平的状态，以及控制单元，其控制第一和第二放电单元，以便基于时钟使能信号来排出第一节点或第二节点。

Patent Agency Ranking