公开(公告)号：US20230208673A1

公开(公告)日：2023-06-29

申请号：US17970186

申请日：2022-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiock SHIN ,  Changhun KIM ,  Sarfaraz AHMED

IPC: H04L12/40 ,  H04L69/324

CPC classification number: H04L12/40 ,  H04L69/324

Abstract: There is provided an electronic apparatus including one or more processor that obtains at least one target node device corresponding to a user command, among the plurality of node devices, and a control command corresponding to the user command, generates an Ethernet frame based on the content and the control command, the Ethernet frame including a data field, and transmits the Ethernet frame to any one of the one or more node devices through the communication interface. The data field includes a content area configured to store information on the content and a plurality of node areas each corresponding to the plurality of node devices, and the control command is stored in a node area corresponding to the at least one target node device among the plurality of node areas.

公开(公告)号：US20240275762A1

公开(公告)日：2024-08-15

申请号：US18637158

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Kiock SHIN ,  Changhun KIM ,  Sarfaraz AHMED

IPC: H04L61/5038 ,  H04L12/40 ,  H04L101/604

CPC classification number: H04L61/5038 ,  H04L12/40 ,  H04L2101/604

Abstract: An electronic device including: a memory configured to store an address code; a communication interface configured to communicate with one or more node apparatuses among a plurality of node apparatuses by serial communication; and a processor configured to: obtain the address code and an address value corresponding to one node apparatus among the one or more node apparatuses, generate an Ethernet frame including a custom field based on the address code and the address value, and transmit the generated Ethernet frame to the one node apparatus through the communication interface, where the custom field includes: an address code area storing the address code and an address value area storing the address value, and the address code configured to set the address value of the one node apparatus.

公开(公告)号：US20240057329A1

公开(公告)日：2024-02-15

申请号：US18338757

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhun KIM ,  Jaeick SON

IPC: H10B41/41 ,  H10B41/27 ,  H10B43/27 ,  H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  G11C16/04 ,  H01L25/065

CPC classification number: H10B41/41 ,  H10B41/27 ,  H10B43/27 ,  H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  G11C16/0483 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A semiconductor device, and more particularly, to a memory device having a three-dimensional structure are provided. The memory device various example embodiments includes a cell region and a peripheral circuit region that at least partially overlaps the cell region when viewed in plan view. The peripheral circuit region includes a first sub-peripheral circuit region including a substrate and a circuit element on the substrate, and a second sub-peripheral circuit region that is stacked on the first sub-peripheral circuit region in a vertical direction and that includes a sub-poly structure and a circuit element on the sub-poly structure.

公开(公告)号：US20230387053A1

公开(公告)日：2023-11-30

申请号：US17983469

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhun KIM ,  Jaeick SON

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/06 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/06515 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/19104 ,  H01L2924/19043 ,  H01L2924/19041

Abstract: A non-volatile memory device includes a first chip including a first substrate and a circuit element, and a second chip stacked on the first chip. The second chip includes a second substrate including a first cell region and a second cell region, gate electrodes stacked on the second cell region of the second substrate, wherein the gate electrodes are between the second substrate and the first chip, an upper insulating layer configured to cover the second substrate, dummy pads and input/output pads on the upper insulating layer, a cover layer on the upper insulating layer to cover the dummy pads, wherein the cover layer is configured to expose the input/output pads to an outside, and dummy contact plugs on one side of the second substrate, wherein the dummy contact plugs are configured to penetrate the upper insulating layer and electrically connect the dummy pads and the circuit element.

公开(公告)号：US20210295794A1

公开(公告)日：2021-09-23

申请号：US17258504

申请日：2019-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhoon LEE ,  Jaemoon LEE ,  Byungkwan KIM ,  Changhun KIM ,  Sungjin LIM

IPC: G09G3/36

Abstract: A display device is disclosed. The display device comprises: a display panel including a plurality of pixels; a gate driver for applying a gate-on signal through a plurality of gate lines of the display panel; a data driver for applying a data signal through a plurality of data lines of the display panel; and a timing controller for controlling the gate driver and the data driver to display an image frame at a first frame frequency, wherein the display panel is driven at a second frame frequency that is higher than the first frame frequency, and the timing controller controls the gate-on signal to be applied to the plurality of gate lines for a time determined on the basis of the second frame frequency, and controls the data driver to apply an over driven data signal to the plurality of data lines.