公开(公告)号：US20190109586A1

公开(公告)日：2019-04-11

申请号：US15981415

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN LEE ,  DAE SEONG LEE ,  MINSU KIM ,  AHREUM KIM ,  CHUNGHEE KIM

IPC: H03K3/037 ,  H03K19/20 ,  G01R31/3177 ,  G01R31/317 ,  G06F1/10

Abstract: An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.

公开(公告)号：US20220375963A1

公开(公告)日：2022-11-24

申请号：US17680907

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE SEONG LEE ,  AH REUM KIM ,  MIN SU KIM

IPC: H01L27/118

Abstract: A semiconductor device includes first, second, and third power rails extending in a first direction on a substrate and sequentially spaced apart in a second direction intersecting the first direction. A fourth power rail extends in the first direction on the substrate between the first and third power rails. A first well of a first conductive type is displaced inside the substrate between the first and third power rails. Cells are continuously displaced between the first and third power rails and share the first well. The first and third power rails are provided with a first voltage, the second power rail is provided with a second voltage different from the first voltage, the fourth power rail is provided with a third voltage different from the first voltage and the second voltage, and the cells are provided with the third voltage from the fourth power rail.