公开(公告)号：US20190109151A1

公开(公告)日：2019-04-11

申请号：US16211496

申请日：2018-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-HYUN KANG ,  HYUN LEE ,  MIN-SU KIM ,  JI-KYUM KIM ,  JONG-WOO KIM

IPC: H01L27/118 ,  G06F17/50

CPC classification number: H01L27/11807 ,  G06F17/505 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

公开(公告)号：US20190109586A1

公开(公告)日：2019-04-11

申请号：US15981415

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN LEE ,  DAE SEONG LEE ,  MINSU KIM ,  AHREUM KIM ,  CHUNGHEE KIM

IPC: H03K3/037 ,  H03K19/20 ,  G01R31/3177 ,  G01R31/317 ,  G06F1/10

Abstract: An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.

公开(公告)号：US20170292993A1

公开(公告)日：2017-10-12

申请号：US15479310

申请日：2017-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DOO-SEOK YOON ,  MIN-SU KIM ,  CHUNG-HEE KIM ,  DAE-SEONG LEE ,  HYUN LEE ,  MATTHEW BERZINS ,  JAMES LIM

IPC: G01R31/3177 ,  G01R31/317 ,  H03K3/037

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/318541 ,  H03K3/0372

Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

公开(公告)号：US20170317100A1

公开(公告)日：2017-11-02

申请号：US15409674

申请日：2017-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-HYUN KANG ,  HYUN LEE ,  MIN-SU KIM ,  JI-KYUM KIM ,  JONG-WOO KIM

IPC: H01L27/118 ,  G06F17/50

CPC classification number: H01L27/11807 ,  G06F17/505 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.