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公开(公告)号:US20220173100A1
公开(公告)日:2022-06-02
申请号:US17536413
申请日:2021-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: AHREUM KIM , SUNGHOON KIM , DAESEOK BYEON
IPC: H01L27/092
Abstract: A semiconductor device includes a substrate, an N-well area formed in the substrate, a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area, and a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate. The first NMOS transistor includes a first N-type active region overlapping each of the substrate and the N-well area, when viewed from above a plane parallel to a top surface of the substrate.
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公开(公告)号:US20220084579A1
公开(公告)日:2022-03-17
申请号:US17239655
申请日:2021-04-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: YOUNGJAE KIM , JINCHEOL KIM , AHREUM KIM , HOMOON SHIN , DOOHO CHO , YONGSUNG CHO
IPC: G11C11/408 , G11C11/4074 , G11C11/4093 , G11C5/06
Abstract: A nonvolatile memory includes; a memory cell array including memory cells commonly connected to a first signal line, a first row decoder including a first pass transistor configured to provide a driving voltage to one end of the first signal line, and a second row decoder including a second pass transistor configured to provide the driving voltage to an opposing end of the first signal line. An ON-resistance of the first pass transistor is different from an ON-resistance of the second pass transistor. A first wiring line having a first resistance connects the first pass transistor and the one end of the first signal line and a second wiring line having a second resistance different from the first resistance connects the second pass transistor and the opposing end of the first signal line.
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公开(公告)号:US20210143820A1
公开(公告)日:2021-05-13
申请号:US16991659
申请日:2020-08-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: YOUNGO LEE , AHREUM KIM , MINSU KIM
IPC: H03K19/00 , H03K17/687 , H03K3/037 , G06F1/08
Abstract: An integrated circuit gating circuit includes a first control stage that outputs a first internal signal based on an enable signal and a clock signal, a second control stage that outputs a second internal signal based on the first internal signal and the clock signal, and an output driver that outputs an output clock signal based on the second internal signal. The second control stage includes a first multi-finger transistor that is connected between a second node outputting the second internal signal and the 0-th node and operates based on the clock signal. A first portion of the first multi-finger transistor is formed in a first row defined on a semiconductor substrate, and a second portion of the first multi-finger transistor is formed in a second row defined on the semiconductor substrate.
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公开(公告)号:US20190109586A1
公开(公告)日:2019-04-11
申请号:US15981415
申请日:2018-05-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYUN LEE , DAE SEONG LEE , MINSU KIM , AHREUM KIM , CHUNGHEE KIM
IPC: H03K3/037 , H03K19/20 , G01R31/3177 , G01R31/317 , G06F1/10
Abstract: An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.
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公开(公告)号:US20240266352A1
公开(公告)日:2024-08-08
申请号:US18638771
申请日:2024-04-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: AHREUM KIM , SUNGHOON KIM , DAESEOK BYEON
IPC: H01L27/092 , H01L21/8238 , H01L25/065 , H01L27/02
CPC classification number: H01L27/0922 , H01L21/823814 , H01L21/823892 , H01L27/0207 , H01L27/092 , H01L27/0925 , H01L25/0657 , H01L2225/06524
Abstract: A semiconductor device includes a substrate, an N-well area formed in the substrate, a first P-channel metal oxide semiconductor (PMOS) transistor having active regions formed in the N-well area, and a first N-channel metal oxide semiconductor (NMOS) transistor having active regions formed in the substrate. The first NMOS transistor includes a first N-type active region overlapping each of the substrate and the N-well area, when viewed from above a plane parallel to a top surface of the substrate.
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公开(公告)号:US20210143800A1
公开(公告)日:2021-05-13
申请号:US16891521
申请日:2020-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JEONGJIN LEE , MINSU KIM , AHREUM KIM
IPC: H03K3/012 , H03K3/3562 , H01L27/092 , G06F30/3953 , G06F30/398 , G06F30/392
Abstract: The present disclosure relates to a hybrid standard cell that includes a semiconductor substrate, a first power rail, a second power rail, a high-speed transistor region and a low-power transistor region. The first power rail and the second power rail are formed above the semiconductor substrate and extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The high-speed transistor region and the low-power transistor region are adjacent to each other in the first direction and arranged in a row region between the first power rail and the second power rail. An operation speed of a high-speed transistor formed in the high-speed transistor region is higher than an operation speed of a low-power transistor formed in the low-power transistor region, and a power consumption of the high-speed transistor is lower than a power consumption of the high-speed transistor.
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公开(公告)号:US20220329234A1
公开(公告)日:2022-10-13
申请号:US17707044
申请日:2022-03-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: AHREUM KIM , YOUNGO LEE , MINSU KIM , EUNHEE CHOI
IPC: H03K3/037 , H03K19/20 , H03K17/687 , G06F30/392
Abstract: A flip-flop includes a first master latch in a first row, a second master latch in a second row, a first slave latch in the first row, and a second slave latch in the second row. The first master latch and the second master latch are adjacently disposed in the second direction, and the first slave latch and the second slave latch are adjacently disposed in the second direction.
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公开(公告)号:US20210194486A1
公开(公告)日:2021-06-24
申请号:US17192360
申请日:2021-03-04
Applicant: SAMSUNG ELECTRONICS CO, LTD.
Inventor: AHREUM KIM
Abstract: A clock gating cell includes an input logic/latch circuit, a keeper logic/signal generating circuit, and an output driver. The input logic/latch circuit generates an internal enable signal based on first and second input enable signals, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic/signal generating circuit is connected between the first node and a second node, includes a feedback path feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes first and second paths discharging the second node. The first and second paths are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.
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