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公开(公告)号:US20160380082A1
公开(公告)日:2016-12-29
申请号:US15138234
申请日:2016-04-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYUN-KWAN YU , DONG-SUK SHIN , WOON-KI SHIN , CHEOL-WOO PARK , RYONG HA , HAN-JIN LIM
IPC: H01L29/66 , H01L21/8234 , H01L21/02 , H01L29/06 , H01L21/3213
CPC classification number: H01L29/66795 , H01L21/02068 , H01L21/32134 , H01L29/66545 , H01L29/7848
Abstract: A method of manufacturing a semiconductor device includes forming an active fin extending longitudinally in a first direction along a surface of a substrate, forming a field insulating layer on the substrate, the field insulating layer covering a part of the active fin, forming a dummy gate electrode on the field insulating layer and the active fin, the dummy gate electrode extending in a second direction different from the first direction, forming a spacer on the sides of the dummy gate electrode, and removing the dummy gate electrode by a wet etching process that includes rinsing the dummy gate electrode intermittently during an etching away of the dummy gate electrode.
Abstract translation: 一种制造半导体器件的方法包括:形成沿衬底表面沿第一方向纵向延伸的有效鳍,在衬底上形成场绝缘层,所述场绝缘层覆盖有源散热片的一部分,形成虚拟栅极 所述虚拟栅极电极沿与第一方向不同的第二方向延伸,在所述虚拟栅电极的侧面形成间隔物,并通过湿式蚀刻工艺除去所述伪栅电极, 包括在伪栅极电极的蚀刻离开期间间歇地冲洗虚拟栅电极。
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公开(公告)号:US20160065215A1
公开(公告)日:2016-03-03
申请号:US14692771
申请日:2015-04-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: DONG-SUK SHIN , JI-YONG AHN , JANG-HYEON LEE
CPC classification number: H03K19/0016 , H03K5/19 , H03L7/18
Abstract: A system on chip includes a plurality of function blocks configured to perform predetermined functions, respectively, a clock control unit configured to generate a plurality of operating clock signals that are provided to the plurality of function blocks, respectively, a clock monitor configured to monitor frequencies of the operating clock signals to generate an interrupt signal, and a processor configured to control the frequencies of the operating clock signals based on the interrupt signal. The clock monitor includes a selector configured to select one of the operating clock signals to provide a selected clock signal, a frequency detector configured to detect a frequency of the selected clock signal to provide a detection frequency, and an interrupt generator configured to generate the interrupt signal based on the detection frequency, where the interrupt signal indicates a frequency abnormality of the operating clock signal corresponding to the selected clock signal.
Abstract translation: 一个片上系统分别包括多个功能块,分别执行预定的功能;时钟控制单元,被配置为产生分别提供给多个功能块的多个工作时钟信号,配置成监视频率的时钟监视器 的操作时钟信号以产生中断信号;以及处理器,被配置为基于所述中断信号来控制所述工作时钟信号的频率。 时钟监视器包括:选择器,被配置为选择一个操作时钟信号以提供所选择的时钟信号;频率检测器,被配置为检测所选择的时钟信号的频率以提供检测频率;以及中断发生器,被配置为产生中断 基于检测频率的信号,其中中断信号指示对应于所选择的时钟信号的操作时钟信号的频率异常。
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公开(公告)号:US20180331105A1
公开(公告)日:2018-11-15
申请号:US16028080
申请日:2018-07-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: KOOK-TAE KIM , HO-SUNG SON , DONG-SUK SHIN , HYUN-JUN SIM , JU-RI LEE , SUNG-UK JANG
IPC: H01L27/092 , H01L29/167 , H01L29/161 , H01L29/16 , H01L21/8238
CPC classification number: H01L27/0924 , H01L21/823814 , H01L21/823821 , H01L27/092 , H01L29/1608 , H01L29/161 , H01L29/167 , H01L29/66545
Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.
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公开(公告)号:US20170271476A1
公开(公告)日:2017-09-21
申请号:US15442871
申请日:2017-02-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SUNG-UK JANG , GI-GWAN PARK , HO-SUNG SON , DONG-SUK SHIN
IPC: H01L29/66 , H01L21/265 , H01L29/78
CPC classification number: H01L29/66545 , H01L21/265 , H01L21/26506 , H01L29/6656 , H01L29/66795 , H01L29/785
Abstract: In a method of manufacturing a semiconductor device, an isolation pattern may be formed on a substrate to define a plurality of active patterns. The active patterns may protrude from the isolation pattern. A preliminary polysilicon layer may be formed on the active patterns to fill a gap between adjacent ones of the active patterns. Ions having no conductivity may be implanted into the preliminary polysilicon layer to form a polysilicon layer having no void. The active patterns maintain their crystalline state during the implanting of the ions. The polysilicon layer may be patterned to form a dummy gate structure on the active pattern. A source/drain region may be formed at an upper portion of the active patterns adjacent to sides of the dummy gate structure.
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公开(公告)号:US20170133379A1
公开(公告)日:2017-05-11
申请号:US15276274
申请日:2016-09-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: KOOK-TAE KIM , HO-SUNG SON , DONG-SUK SHIN , HYUN-JUN SIM , JU-RI LEE , SUNG-UK JANG
IPC: H01L27/092 , H01L29/161 , H01L29/16 , H01L29/167
CPC classification number: H01L27/0924 , H01L21/26586 , H01L21/823814 , H01L21/823821 , H01L27/092 , H01L29/1608 , H01L29/161 , H01L29/167 , H01L29/7851
Abstract: A dummy gate electrode layer and a dummy gate mask layer may be formed on a substrate. The dummy gate mask layer may be patterned to form a dummy gate mask so that a portion of the dummy gate electrode layer is exposed. Ions may be implanted into the exposed portion of the dummy gate electrode layer and a portion of the dummy gate electrode layer adjacent thereto by an angled ion implantation to form a growth blocking layer in the dummy gate electrode layer. The dummy gate electrode layer may be etched using the dummy gate mask as an etching mask to form a dummy gate electrode. A spacer may be formed on side surfaces of a dummy gate structure including the dummy gate electrode and the dummy gate mask. An SEG process may be performed to form an epitaxial layer.
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