公开(公告)号：US11974440B2

公开(公告)日：2024-04-30

申请号：US17219299

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsung Cho ,  Inho Kang ,  Ansoo Park ,  Jeunghwan Park ,  Dongha Shin ,  Jeawon Jeong

IPC: G11C11/00 ,  G06F3/06 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/40 ,  G06F3/0656 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit provided in a page buffer region including a main region and a cache region provided in a first horizontal direction, and including a first page buffer unit and a second page buffer unit adjacent to each other in a second horizontal direction in the main region. A first sensing node of the first page buffer unit includes a first lower metal pattern, and a first upper metal pattern, and electrically connected to the first lower metal pattern. A second sensing node of the second page buffer unit includes a second lower metal pattern, and a second upper metal pattern, electrically connected to the second lower metal pattern, and not adjacent to the first upper metal pattern in the second horizontal direction.

公开(公告)号：US11887672B2

公开(公告)日：2024-01-30

申请号：US17693013

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-Woo Lee ,  Seungyeon Kim ,  Dongha Shin ,  Beakhyung Cho

IPC: G11C16/16 ,  G11C16/24 ,  G11C16/30 ,  G11C16/28 ,  G11C7/10

CPC classification number: G11C16/16 ,  G11C7/1039 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A nonvolatile memory device includes a plurality of bit lines that is connected with a plurality of cell strings, a common source line that is connected with the plurality of cell strings, at least one dummy bit line that is provided between the common source line and the plurality of bit lines, a control logic circuit that generates at least one dummy bit line driving signal in response to a command from an external device, and a dummy bit line driver that selectively provides a first voltage to the at least one dummy bit line in response to the dummy bit line driving signal.

公开(公告)号：US11830805B2

公开(公告)日：2023-11-28

申请号：US17212222

申请日：2021-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongha Shin ,  Jeawon Jeong ,  Bongsoon Lim

IPC: H01L23/522 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A vertical memory device includes a plurality of word lines on a substrate, a plurality of word line cut regions extending parallel to each other, a memory cell array comprising a plurality of channel structures extending on the substrate through the plurality of word lines and arranged in a honeycomb structure, a plurality of contacts on the plurality of channel structures, and a plurality of bit lines connected to the plurality of channel structures through the plurality of contacts. The memory cell array comprises a first sub-array and a second sub-array, which are defined by the plurality of word line cut regions and are connected to some identical bit lines from among the plurality of bit lines, and a layout of contacts in the first sub-array from among the plurality of contacts is different from a layout of contacts in the second sub-array from among the plurality of contacts.

公开(公告)号：US11557599B2

公开(公告)日：2023-01-17

申请号：US16911299

申请日：2020-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongha Shin ,  Yohan Lee

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  G11C16/04 ,  H01L27/1157

Abstract: A nonvolatile memory device includes; a memory cell area including a cell structure and a common source plate. The memory cell area is mounted on a peripheral circuit area including a buried area covered by the memory cell area and an exposed area uncovered by the memory cell area. A first peripheral circuit (PC) via extending from the exposed area, and a common source (CS) via extending from the common source plate, wherein the first PC via and the CS via are connected by a CS wire disposed outside the cell structure and providing a bias voltage to the common source plate.