公开(公告)号：US11742351B2

公开(公告)日：2023-08-29

申请号：US17384920

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US11675973B2

公开(公告)日：2023-06-13

申请号：US17102679

申请日：2020-11-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sejung Kwon ,  Dongsoo Lee

IPC: G06F40/205 ,  G06N3/04 ,  G06F12/0813 ,  G06F40/237

CPC classification number: G06F40/205 ,  G06F12/0813 ,  G06F40/237 ,  G06N3/04

Abstract: An electronic device is provided. The electronic device includes a first memory configured to operate at a first speed and store compressed vectors corresponding to words, and scaling factors corresponding to the compressed vectors; a second memory that is faster than the first memory and is configured to store a first group of the compressed vectors, and store a first group of the scaling factors; and a processor configured to obtain a first compressed vector and a first scaling factor corresponding to an input word from the first memory or the second memory and process the obtained first compressed vector and the obtained first scaling factor by using a neural network.

公开(公告)号：US11335680B2

公开(公告)日：2022-05-17

申请号：US16912427

申请日：2020-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Seungha Oh ,  Rakhwan Kim ,  Minjung Park ,  Dongsoo Lee

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

公开(公告)号：US20200035801A1

公开(公告)日：2020-01-30

申请号：US16592309

申请日：2019-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Jae-Jung Kim ,  Jinkyu Jang ,  Sangyong Kim ,  Hoonjoo Na ,  Dongsoo Lee ,  Sangjin Hyun

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/775 ,  H01L27/11 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

公开(公告)号：US11990473B2

公开(公告)日：2024-05-21

申请号：US17723532

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Seungha Oh ,  Rakhwan Kim ,  Minjung Park ,  Dongsoo Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

公开(公告)号：US11734577B2

公开(公告)日：2023-08-22

申请号：US16876688

申请日：2020-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sejung Kwon ,  Dongsoo Lee

IPC: G06N3/10 ,  G06F17/16

CPC classification number: G06N3/10 ,  G06F17/16

Abstract: A method for an electronic apparatus to perform an operation of an artificial intelligence model includes acquiring resource information for hardware of the electronic apparatus while a plurality of data used for an operation of a neural network model are stored in a memory, the plurality of data respectively having degrees of importance different from each other; obtaining data to be used for the operation of the neural network model among the plurality of data according to the degrees of importance of each of the plurality of data based on the acquired resource information; and performing the operation of the neural network model by using the obtained data.

公开(公告)号：US11568254B2

公开(公告)日：2023-01-31

申请号：US16727323

申请日：2019-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongsoo Lee ,  Sejung Kwon ,  Parichay Kapoor ,  Byeoungwook Kim

IPC: G06N3/08 ,  G06F17/16 ,  G06N3/04

Abstract: An electronic apparatus is provided. The electronic apparatus includes sample data and memory storing a first matrix included in an artificial intelligence model trained based on sample data, and a processor configured to prunes each of a plurality of first elements included in the first matrix based on a first threshold, and acquire a first pruning index matrix that indicates whether each of the plurality of first elements has been pruned with binary data, factorize the first matrix to a second matrix of which size was determined based on the number of rows and the rank, and a third matrix of which size was determined based on the rank and the number of columns of the first matrix, prunes each of a plurality of second elements included in the second matrix based on a second threshold, and acquire a second pruning index matrix that indicates whether each of the plurality of second elements has been pruned with binary data, prunes each of a plurality of third elements included in the third matrix based on a third threshold, and acquire a third pruning index matrix that indicates whether each of the plurality of third elements has been pruned with binary data, acquire a final index matrix based on the second pruning index matrix and the third pruning index matrix, and update at least one of the second pruning index matrix or the third pruning index matrix by comparing the final index matrix with the first pruning index matrix.

公开(公告)号：US11121131B2

公开(公告)日：2021-09-14

申请号：US16592330

申请日：2019-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8238

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US10461167B2

公开(公告)日：2019-10-29

申请号：US15861949

申请日：2018-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L21/82 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/36

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US12021080B2

公开(公告)日：2024-06-25

申请号：US18353214

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.