公开(公告)号：US20220253283A1

公开(公告)日：2022-08-11

申请号：US17563836

申请日：2021-12-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaewoo Seo ,  Minjae Jeong ,  Yongdurk Kim ,  Giyoung Yang ,  Eungchul Jun ,  Changbeom Kim ,  Moogyu Bae

IPC分类号： G06F7/505 ,  H03K17/687 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

摘要： A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied and a plurality of second gate lines to which the second input signal is applied, wherein at least one of a first circuit area and a second circuit area is arranged in a first row, at least one of a third circuit area and a fourth circuit area is arranged in a second row parallel with the first row, and a first gate line of a circuit area arranged in the first row is aligned with a first gate line of a circuit area arranged in the second row