公开(公告)号：US20240243117A1

公开(公告)日：2024-07-18

申请号：US18412177

申请日：2024-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongeun Cho ,  Eunhee Choi ,  Kibum Kim ,  Seonkyeong Kim ,  Hayoung Kim ,  Hyunjeong Roh ,  Moogyu Bae

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L27/0928 ,  H01L27/0924

Abstract: An integrated circuit includes a first region having a plurality of first cells arranged in first rows extending in a first direction and a plurality of first gate electrodes extending in a second direction that crosses the first direction, a second region having a plurality of second cells arranged in second rows extending in the first direction and a plurality of second gate electrodes extending in the second direction, and a third region between the first region and the second region and having a plurality of third gate electrodes extending in the second direction. A second height of each of the second rows is greater than a first height of each of the first rows. A pitch of the first gate electrodes, a pitch of the second gate electrodes, and a pitch of the third gate electrodes are the same.

公开(公告)号：US20220253283A1

公开(公告)日：2022-08-11

申请号：US17563836

申请日：2021-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewoo Seo ,  Minjae Jeong ,  Yongdurk Kim ,  Giyoung Yang ,  Eungchul Jun ,  Changbeom Kim ,  Moogyu Bae

IPC: G06F7/505 ,  H03K17/687 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied and a plurality of second gate lines to which the second input signal is applied, wherein at least one of a first circuit area and a second circuit area is arranged in a first row, at least one of a third circuit area and a fourth circuit area is arranged in a second row parallel with the first row, and a first gate line of a circuit area arranged in the first row is aligned with a first gate line of a circuit area arranged in the second row