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公开(公告)号：US10134838B2
公开(公告)日：2018-11-20
申请号：US15820053
申请日：2017-11-21
发明人： Myoung-Ho Kang , Jung-Ho Do , Giyoung Yang , Seungyoung Lee
IPC分类号： H01L29/06 , H01L27/092 , H01L29/08 , H01L21/8238 , H01L29/78
摘要： A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper portion of the substrate that includes a PMOSFET region and an NMOSFET region, and a gate electrode that extends across the active patterns in a first direction that crosses the second direction. The active patterns extend across the PMOSFET region and the NMOSFET region. The third device isolation layer lies between the PMOSFET region and the NMOSFET region. The third device isolation layer comprises a first part that extends in the second direction and a second part that extends in a third direction that crosses the first and second directions. The second part has opposite sidewalls parallel to the third direction, in a plan view.
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公开(公告)号：US10037401B2
公开(公告)日：2018-07-31
申请号：US15896415
申请日：2018-02-14
发明人： Taejoong Song , Sanghoon Baek , Sungwe Cho , Jung-Ho Do , Giyoung Yang , Jinyoung Lim
IPC分类号： G06F17/50 , H01L27/118 , H01L27/02
CPC分类号： G06F17/5077 , H01L27/0207 , H01L27/11807
摘要： A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.
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公开(公告)号：US20240061039A1
公开(公告)日：2024-02-22
申请号：US18194643
申请日：2023-04-02
发明人： Byounggon Kang , Dalhee Lee , Giyoung Yang , Minji Kim , Taejung Seol , Jaebeom Yang
IPC分类号： G01R31/3185 , G01R31/317
CPC分类号： G01R31/318525 , G01R31/318541 , G01R31/31725
摘要： A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.
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公开(公告)号：US20220058327A1
公开(公告)日：2022-02-24
申请号：US17361854
申请日：2021-06-29
发明人： Giyoung Yang , Ingyum Kim
IPC分类号： G06F30/392 , H01L27/088 , G06F30/396
摘要： A semiconductor device includes a substrate having an active region, first standard cells arranged in a first row on the active region, second standard cells arranged in a second row on the active region and having a first boundary with the first standard cells, a third standard cells arranged in a third row on the active region and having a second boundary with the first standard cells, and a plurality of power supply lines, respectively arranged along boundaries. Each of the first to third standard cells includes a plurality of fin patterns extending in the first direction, and the plurality of fin patterns are arranged in a second direction, so as not to be disposed on at least one boundary, among the first and second boundaries.
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公开(公告)号：US12044733B2
公开(公告)日：2024-07-23
申请号：US18194643
申请日：2023-04-02
发明人： Byounggon Kang , Dalhee Lee , Giyoung Yang , Minji Kim , Taejung Seol , Jaebeom Yang
IPC分类号： G01R31/3185 , G01R31/317
CPC分类号： G01R31/318525 , G01R31/31725 , G01R31/318541
摘要： A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.
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公开(公告)号：US11948932B2
公开(公告)日：2024-04-02
申请号：US17528242
申请日：2021-11-17
发明人： Hakchul Jung , Ingyum Kim , Giyoung Yang , Jaewoo Seo
IPC分类号： H01L27/02 , H01L29/06 , H01L29/423 , H01L29/786
CPC分类号： H01L27/0207 , H01L29/0665 , H01L29/42392 , H01L29/78696
摘要： An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.
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公开(公告)号：US20220253283A1
公开(公告)日：2022-08-11
申请号：US17563836
申请日：2021-12-28
发明人： Jaewoo Seo , Minjae Jeong , Yongdurk Kim , Giyoung Yang , Eungchul Jun , Changbeom Kim , Moogyu Bae
IPC分类号： G06F7/505 , H03K17/687 , H01L27/02 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786
摘要： A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied and a plurality of second gate lines to which the second input signal is applied, wherein at least one of a first circuit area and a second circuit area is arranged in a first row, at least one of a third circuit area and a fourth circuit area is arranged in a second row parallel with the first row, and a first gate line of a circuit area arranged in the first row is aligned with a first gate line of a circuit area arranged in the second row
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公开(公告)号：US10541243B2
公开(公告)日：2020-01-21
申请号：US15355159
申请日：2016-11-18
发明人： Jung-Ho Do , Seungyoung Lee , Jonghoon Jung , Jinyoung Lim , Giyoung Yang , Sanghoon Baek , Taejoong Song
IPC分类号： H01L27/11 , H01L23/522 , H01L23/485
摘要： A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.
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公开(公告)号：US09536946B2
公开(公告)日：2017-01-03
申请号：US14833983
申请日：2015-08-24
发明人： Jae-Ho Park , Taejoong Song , Sanghoon Baek , Jintae Kim , Giyoung Yang , Hyosig Won
IPC分类号： H01L27/088 , H01L29/06 , H01L29/08 , H01L29/417 , H01L27/02 , H01L27/092 , H01L21/8238
CPC分类号： H01L29/0642 , H01L21/768 , H01L21/76816 , H01L21/823871 , H01L27/0207 , H01L27/092 , H01L27/0924 , H01L29/0847 , H01L29/41758 , H01L29/41791
摘要： A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact.
摘要翻译： 半导体器件包括具有有源区的衬底，与有源区相交且在平行于衬底顶表面的第一方向上延伸的栅极结构，设置在有源区中的第一源极/漏极区和第二源极/漏极区 分别与第一源极/漏极区域和第二源极/漏极区域接触的第一修改触点和第二修改触点。 栅极结构和第一改性接触之间的距离小于栅极结构和第二改性接触之间的距离。
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公开(公告)号：US20240203973A1
公开(公告)日：2024-06-20
申请号：US18591089
申请日：2024-02-29
发明人： Hakchul Jung , Ingyum Kim , Giyoung Yang , Jaewoo Seo
IPC分类号： H01L27/02 , H01L29/06 , H01L29/423 , H01L29/786
CPC分类号： H01L27/0207 , H01L29/0665 , H01L29/42392 , H01L29/78696
摘要： An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.
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