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公开(公告)号：US11996854B2
公开(公告)日：2024-05-28
申请号：US17895393
申请日：2022-08-25
CPC分类号： H03L7/091 , H03L7/0891 , H03L7/099
摘要： A sub-sampling phase lock loop includes samplers that obtain sampled values by sampling clock signal phases corresponding to a clock signal generated by a voltage controlled oscillator at sampling edges of reference signal phases of a reference signal generated by a reference clock generator over a reference clock cycle; and a phase detector that selects a phase for a particular instant of the reference signal based on at least one sampled value satisfying a predetermined criteria, the phase corresponding to a clock signal phase value and a reference signal phase value respectively selected from the clock signal and reference signal phases, the phase detector tracks the selected phase at every successive instant of the reference signal, and determines a sampled value associated with the selected phase in every successive instant of the reference signal; and a processing unit that acquires frequency information based on the tracking of the selected phase.
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公开(公告)号：US11804945B2
公开(公告)日：2023-10-31
申请号：US17669262
申请日：2022-02-10
发明人： Juyun Lee , Vishnu Kalyanamahadevi Gopalan Jawarlal , Kang Jik Kim , Hyo Gyuem Rhew , Jae Hyun Park
CPC分类号： H04L7/0016 , H03L7/0807
摘要： A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.
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公开(公告)号：US11728792B2
公开(公告)日：2023-08-15
申请号：US17706191
申请日：2022-03-28
IPC分类号： H03K3/017
CPC分类号： H03K3/017
摘要： An apparatus for in-phase and quadrature phase (“IQ”) generation comprises a CMOS clock distributor for providing a clock input. A first IQ divider circuit is configured for receiving the clock input and dividing the clock input into in-phase and quadrature phase (IQ) output. A clock processing circuit is configured for processing the clock input. A second IQ divider circuit is configured for receiving the processed clock input and dividing the processed clock input into in-phase and quadrature phase (IQ) output. A multiplexer circuit is coupled to the first IQ divider circuit and the second IQ divider circuit for selecting the IQ output from the first IQ divider circuit or the second IQ divider circuit.
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4.发明授权公开(公告)号：US11601116B2
公开(公告)日：2023-03-07
申请号：US17307489
申请日：2021-05-04
摘要： A system for generating a sub-harmonically injection locked phase interpolated output signal. The system comprises ring oscillator (RO) circuitry to generate an output oscillator signal in response to a periodic input signal. The RO circuitry includes a plurality of differential delay RO stages interconnected in cascade within a closed loop, where each RO stage is configured to establish a corresponding delayed version of the output oscillator signal successively shifted in phase by a predetermined phase difference based on a predetermined interpolation mapping scheme. The system further comprises signal injection circuitry coupled to the RO circuitry to apply a first signal having a first input phase and a second signal having a second input phase to the plurality of differential delay RO stages based on the predetermined interpolation mapping scheme to lock a frequency of the output oscillator signal at one half the frequency of the periodic input signal.
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公开(公告)号：US11909407B2
公开(公告)日：2024-02-20
申请号：US17947845
申请日：2022-09-19
发明人： Praveen Rathee , Vishnu Kalyanamahadevi Gopalan Jawarlal , Sanjeeb Kumar Ghosh , Avneesh Singh Verma
摘要： A system and method to dynamically control a reset signal for an IQ divider are provided. The system includes an IQ divider configured to output a IQ divider output clock; an input configured to receive a reference clock; a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit including an automatic frequency calibration (AFC) logic; and a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.
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公开(公告)号：US20230138296A1
公开(公告)日：2023-05-04
申请号：US17669262
申请日：2022-02-10
发明人： Juyun LEE , Vishnu Kalyanamahadevi Gopalan Jawarlal , Kang Jik KIM , Hyo Gyuem RHEW , Jae Hyun PARK
摘要： A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.
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公开(公告)号：US20220231676A1
公开(公告)日：2022-07-21
申请号：US17352516
申请日：2021-06-21
发明人： Vishnu Kalyanamahadevi Gopalan Jawarlal , Gunjan Mandal , Avneesh Singh Verma , Sanjeeb Kumar Ghosh
摘要： An integrated circuit device includes a sensing circuit configured to determine a delay code from a plurality of delay codes using a phase interpolation (PI) code and a plurality of input clock phases, a variable delay circuit coupled to the sensing circuit and configured to generate a variable delay based on the delay code and generate a delayed PI code using the PI code and the delay code, the delayed PI code corresponding to a code obtained from adding the variable delay to the PI code, and a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the plurality of input clock phases using the delayed PI code.
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8.发明公开公开(公告)号：US20230421343A1
公开(公告)日：2023-12-28
申请号：US18243442
申请日：2023-09-07
发明人： Juyun LEE , Vishnu Kalyanamahadevi Gopalan Jawarlal , Kang Jik KIM , Hyo Gyuem RHEW , Jae Hyun PARK
CPC分类号： H04L7/0016 , H03L7/0807
摘要： A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.
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公开(公告)号：US11469746B2
公开(公告)日：2022-10-11
申请号：US17352516
申请日：2021-06-21
发明人： Vishnu Kalyanamahadevi Gopalan Jawarlal , Gunjan Mandal , Avneesh Singh Verma , Sanjeeb Kumar Ghosh
摘要： An integrated circuit device includes a sensing circuit configured to determine a delay code from a plurality of delay codes using a phase interpolation (PI) code and a plurality of input clock phases, a variable delay circuit coupled to the sensing circuit and configured to generate a variable delay based on the delay code and generate a delayed PI code using the PI code and the delay code, the delayed PI code corresponding to a code obtained from adding the variable delay to the PI code, and a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the plurality of input clock phases using the delayed PI code.
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公开(公告)号：US10917076B1
公开(公告)日：2021-02-09
申请号：US16818174
申请日：2020-03-13
发明人： Vishnu Kalyanamahadevi Gopalan Jawarlal , Tamal Das , Avneesh Singh Verma , Sanjeeb Kumar Ghosh
摘要： A ring oscillator includes at least one oscillator stage having a first output and a second output and a start-up circuit. The start-up circuit includes a plurality of AC coupling capacitors receiving the first output and the second output, and a plurality of switches connected to the AC coupling capacitors. The start-up circuit is configured to provide a differential start-up voltage to at least one node of the oscillator using the plurality of switches and the AC coupling capacitors.
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