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公开(公告)号：US11437382B2
公开(公告)日：2022-09-06
申请号：US16916366
申请日：2020-06-30
发明人： Hyunji Song , Jaehoon Kim , Kwangho Park , Yonghoon Son , Gyeonghee Lee , Seungjae Jung
IPC分类号： H01L27/108
摘要： An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.
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公开(公告)号：US12127396B2
公开(公告)日：2024-10-22
申请号：US17874512
申请日：2022-07-27
发明人： Hyunji Song , Jaehoon Kim , Kwangho Park , Yonghoon Son , Gyeonghee Lee , Seungjae Jung
IPC分类号： H10B12/00
CPC分类号： H10B12/373 , H10B12/0387
摘要： An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.
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公开(公告)号：US11751379B2
公开(公告)日：2023-09-05
申请号：US17731611
申请日：2022-04-28
发明人： Jae Hoon Kim , Kwang-Ho Park , Yong-Hoon Son , Hyunji Song , Gyeonghee Lee , Seungjae Jung
IPC分类号： G11C5/06 , H10B12/00 , G11C11/4097
CPC分类号： H10B12/30 , G11C11/4097
摘要： A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.
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公开(公告)号：US11462554B2
公开(公告)日：2022-10-04
申请号：US16857507
申请日：2020-04-24
发明人： Yong-Hoon Son , Jae Hoon Kim , Kwang-ho Park , Hyunji Song , Gyeonghee Lee , Seungjae Jung
IPC分类号： H01L27/11565 , H01L27/11573 , H01L27/1157 , H01L23/528 , H01L23/522 , H01L27/11582
摘要： A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.
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公开(公告)号：US11348924B2
公开(公告)日：2022-05-31
申请号：US16923572
申请日：2020-07-08
发明人： Jae Hoon Kim , Kwang-Ho Park , Yong-Hoon Son , Hyunji Song , Gyeonghee Lee , Seungjae Jung
IPC分类号： G11C5/06 , H01L27/108 , G11C11/4097
摘要： A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.
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