公开(公告)号：US11282921B2

公开(公告)日：2022-03-22

申请号：US16903015

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuhwan Ahn ,  Sung Soo Kim ,  Chaeho Na ,  Woongsik Nam ,  Donghyun Roh

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.

公开(公告)号：US12080767B2

公开(公告)日：2024-09-03

申请号：US17406310

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Soo Kim ,  Joohan Kim ,  Gyuhwan Ahn ,  Ik Soo Kim ,  Jongmin Baek

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/7851 ,  H01L29/7853

Abstract: A semiconductor device includes a first active pattern disposed on a substrate, a device isolation layer filling a trench that defines the first active pattern, a first channel pattern and a first source/drain pattern disposed on the first active pattern in which the first channel pattern includes semiconductor patterns stacked and spaced apart from each other, a gate electrode that extends and runs across the first channel pattern, a gate dielectric layer disposed between the first channel pattern and the gate electrode, and a first passivation pattern disposed between the device isolation layer and a first sidewall of the first active pattern. The first passivation pattern includes an upper part that protrudes upwardly from the device isolation layer, and a lower part buried in the device isolation layer. The gate dielectric layer covers the upper part of the first passivation pattern.

公开(公告)号：US12034042B2

公开(公告)日：2024-07-09

申请号：US18350187

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuhwan Ahn ,  Sung Soo Kim ,  Chaeho Na ,  Woongsik Nam ,  Donghyun Roh

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0653 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.

公开(公告)号：US11735626B2

公开(公告)日：2023-08-22

申请号：US17667996

申请日：2022-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuhwan Ahn ,  Sung Soo Kim ,  Chaeho Na ,  Woongsik Nam ,  Donghyun Roh

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.