公开(公告)号：US11282921B2

公开(公告)日：2022-03-22

申请号：US16903015

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuhwan Ahn ,  Sung Soo Kim ,  Chaeho Na ,  Woongsik Nam ,  Donghyun Roh

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.

公开(公告)号：US11670676B2

公开(公告)日：2023-06-06

申请号：US17379051

申请日：2021-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki Min ,  Donghyun Roh ,  Chaeho Na

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092

Abstract: An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

公开(公告)号：US20240258399A1

公开(公告)日：2024-08-01

申请号：US18471260

申请日：2023-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaeho Na ,  Sangkoo Kang ,  Donghyun Roh ,  Dahye Kim

IPC: H01L29/49 ,  H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/4983 ,  H01L21/02126 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775

Abstract: An integrated circuit device includes a gate line disposed on a fin-type active region, a source/drain region disposed on the fin-type active region, and an insulating spacer structure that covers the gate line and the source/drain region. The insulating spacer structure includes a first spacer portion that covers the sidewall of the gate line, a second spacer portion integrally connected to the first spacer portion, where the second spacer portion protrudes in a first lateral direction and covers a partial region of a sidewall of the source/drain region, and a spacer corner portion that fills a corner space defined by the gate line and the source/drain region between the first spacer portion and the second spacer portion. The insulating spacer structure has a single film structure that includes a SiOC film doped with about 0 at % to about 5 at % of nitrogen atoms.

公开(公告)号：US20230261047A1

公开(公告)日：2023-08-17

申请号：US18307074

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki Min ,  Donghyun Roh ,  Chaeho Na

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L27/088 ,  H01L27/092 ,  H01L21/823878 ,  H01L21/823481

Abstract: An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

公开(公告)号：US20250133791A1

公开(公告)日：2025-04-24

申请号：US18741416

申请日：2024-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaeho Na ,  Sangkoo Kang ,  Sunki Min

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a first fin-type active region and a second fin-type active region, each extending on a substrate in a first horizontal direction, a plurality of gate lines on the first fin-type active region and second fin-type active region, the plurality of gate lines extending in a second horizontal direction that crosses the first horizontal direction, a first source/drain region and a second source/drain region respectively in the first fin-type active region and second fin-type active region, wherein each of the first source/drain region and the second source/drain region is disposed between the plurality of gate lines, a spacer structure disposed on the plurality of gate lines, the first source/drain region and the second source/drain region, and a protective insulating film disposed on the second source/drain region and exposing the first source/drain region.

公开(公告)号：US12107122B2

公开(公告)日：2024-10-01

申请号：US18307074

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki Min ,  Donghyun Roh ,  Chaeho Na

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/0649 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092

Abstract: An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

公开(公告)号：US12034042B2

公开(公告)日：2024-07-09

申请号：US18350187

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuhwan Ahn ,  Sung Soo Kim ,  Chaeho Na ,  Woongsik Nam ,  Donghyun Roh

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0653 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.

公开(公告)号：US11735626B2

公开(公告)日：2023-08-22

申请号：US17667996

申请日：2022-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuhwan Ahn ,  Sung Soo Kim ,  Chaeho Na ,  Woongsik Nam ,  Donghyun Roh

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.