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    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS 有权

    公开(公告)号：US20210149764A1

    公开(公告)日：2021-05-20

    申请号：US17137535

    申请日：2020-12-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HOI-JU CHUNG ,  SANG-UHN CHA ,  HO-YOUNG SONG ,  HYUN-JOONG KIM

    IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

    ANTI-FUSE CIRCUIT IN WHICH ANTI-FUSE CELL DATA IS MONITORED, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    3.
    发明申请
    ANTI-FUSE CIRCUIT IN WHICH ANTI-FUSE CELL DATA IS MONITORED, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
    监测防细胞细胞数据的防静电电路，以及包括其中的半导体器件

    公开(公告)号：US20130294140A1

    公开(公告)日：2013-11-07

    申请号：US13793457

    申请日：2013-03-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JONG-MIN OH ,  HO-YOUNG SONG ,  SEONG-JIN JANG

    IPC: G11C17/16

    CPC classification number: G11C17/16 ,  G11C29/76

    Abstract: An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal.

    Abstract translation: 公开了一种其中可以在反熔丝电路外面监视反熔丝程序数据的反熔丝电路和包括反熔丝电路的半导体器件。 反熔丝电路包括反熔丝阵列，数据存储电路和第一选择电路。 反熔丝阵列包括一个或多个抗熔丝块，其包括具有多个反熔丝单元的第一反熔丝块，并且反熔丝阵列被配置为存储反熔丝程序数据。 数据存储电路被配置为通过一个或多个数据总线接收并存储来自反熔丝阵列的反熔丝程序数据。 第一选择电路被配置为响应于第一选择信号输出所述一个或多个反熔丝块的所选反熔丝块的反熔丝程序数据。

    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20200301779A1

    公开(公告)日：2020-09-24

    申请号：US16894115

    申请日：2020-06-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HOI-JU CHUNG ,  SANG-UHN CHA ,  HO-YOUNG SONG ,  HYUN-JOONG KIM

    IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

    STACK SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING SAME
    6.
    发明申请
    STACK SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING SAME 有权
    堆叠半导体器件和包括其的存储器件

    公开(公告)号：US20160133312A1

    公开(公告)日：2016-05-12

    申请号：US14790451

    申请日：2015-07-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HAE-SUK LEE ,  KYO-MIN SOHN ,  HO-YOUNG SONG ,  SANG-HOON SHIN ,  HAN-VIT JUNG

    IPC: G11C11/4093 ,  G11C11/4096 ,  H01L25/065 ,  G11C11/4094

    CPC classification number: H01L25/0657 ,  G11C7/1066 ,  G11C7/1069 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A memory device including a stack semiconductor device including; an upper substrate vertically stacked on a lower substrate, the upper substrate including N upper through-silicon vias (UTSV) and upper driving circuits, and the lower substrate including N lower through-silicon vias (LTSV) and lower driving circuits, wherein each one of the upper driving circuits is stagger-connected between a Kth UTSV and a (K+1)th LTSV, where ‘N’ is a natural number greater than 1, and ‘K’ is a natural number ranging from 1 to (N−1).

    Abstract translation: 一种包括堆叠半导体器件的存储器件，包括： 垂直堆叠在下基板上的上基板，上基板包括N个上穿通硅通孔（UTSV）和上驱动电路，下基板包括N个下穿通硅通孔（LTSV）和下驱动电路，其中每个 的上驱动电路在第K个UTSV和第（K + 1）个LTSV之间错开连接，其中'N'是大于1的自然数，'K'是从1到（N- 1）。

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