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公开(公告)号:US20210288054A1
公开(公告)日:2021-09-16
申请号:US17032277
申请日:2020-09-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYOJOON RYU , KWANYONG KIM , SEOGOO KANG , SUNIL SHIM , WONSEOK CHO , JEEHON HAN
IPC: H01L27/1157 , H01L23/522 , H01L27/11565 , H01L27/11582 , H01L27/11573
Abstract: A semiconductor device includes; a memory stack disposed on a substrate and including a lower gate electrode, an upper gate stack including a string selection line, a vertically extending memory gate contact disposed on the lower gate electrode, and a vertically extending selection line stud disposed on the string selection line. The string selection line includes a material different from that of the lower gate electrode, and the selection line stud includes a material different from that of the memory gate contact.
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公开(公告)号:US20230180478A1
公开(公告)日:2023-06-08
申请号:US18103070
申请日:2023-01-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYOJOON RYU , YOUNGHWAN SON , SEOGOO KANG , JESUK MOON , JUNGHOON JUN , KOHJI KANAMORI , JEEHOON HAN
Abstract: A semiconductor device includes; gate layers stacked on a substrate, a channel layer extending through the gate layers, a string select gate layer disposed on the channel layer and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer including a second protruding region.
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公开(公告)号:US20230262984A1
公开(公告)日:2023-08-17
申请号:US18138189
申请日:2023-04-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYOJOON RYU , KWANYONG KIM , SEOGOO KANG , SUNIL SHIM , WONSEOK CHO , JEEHON HAN
IPC: H10B43/35 , H01L23/522 , H10B43/10 , H10B43/27 , H10B43/40
CPC classification number: H10B43/35 , H01L23/5226 , H10B43/10 , H10B43/27 , H10B43/40
Abstract: A semiconductor device includes; a memory stack disposed on a substrate and including a lower gate electrode, an upper gate stack including a string selection line, a vertically extending memory gate contact disposed on the lower gate electrode, and a vertically extending selection line stud disposed on the string selection line. The string selection line includes a material different from that of the lower gate electrode, and the selection line stud includes a material different from that of the memory gate contact.
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公开(公告)号:US20210143160A1
公开(公告)日:2021-05-13
申请号:US16942456
申请日:2020-07-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: HYOJOON RYU , YOUNGHWAN SON , SEOGOO KANG , JESUK MOON , JUNGHOON JUN , KOHJI KANAMORI , JEEHOON HAN
IPC: H01L27/1157 , H01L27/11565 , H01L27/11582 , H01L27/11573
Abstract: A semiconductor device includes; gate layers stacked on a substrate, a channel layer extending through the gate layers, a string select gate layer disposed on the channel layer and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer including a second protruding region.
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