公开(公告)号：US20240324181A1

公开(公告)日：2024-09-26

申请号：US18469791

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Kim ,  Ho-Ju Song ,  Myeong-Dong Lee

IPC: H10B12/00 ,  H01L21/768 ,  H01L23/528

CPC classification number: H10B12/482 ,  H01L21/76877 ,  H01L23/528 ,  H10B12/03 ,  H10B12/485

Abstract: A method of manufacturing a semiconductor device includes forming a buffer layer on a substrate including active regions and word lines, sequentially stacking a first conductive layer and a first insulating layer, forming bit line structure main parts such that each bit line main part is in contact with one or more of the active regions through a plurality of first contacts, by etching the first insulating layer and the first conductive layer, stacking first spacers, forming bit line structure expansions by etching the first spacers, the first insulating layer, and the first conductive layer, and forming second contacts such that the second contacts are in contact with the active regions, respectively. The bit line structure expansions are connected to the bit line structure main parts, respectively, and are wider than the bit line structure main parts as viewed in a plan view.

公开(公告)号：US11251188B2

公开(公告)日：2022-02-15

申请号：US16990305

申请日：2020-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Hyun Kim ,  Joon Young Kang ,  Youngjun Kim ,  Jinhyung Park ,  Ho-Ju Song ,  Sang-Jun Lee ,  Hyeran Lee ,  Bong-Soo Kim ,  Sungwoo Kim

IPC: H01L27/088 ,  H01L21/00 ,  H01L27/108

Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.