公开(公告)号：US10727826B2

公开(公告)日：2020-07-28

申请号：US16282870

申请日：2019-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hun-Dae Choi ,  Hwa-Pyong Kim

IPC: H03K5/156 ,  G11C11/4076 ,  H03L7/081 ,  H03L7/089 ,  H03L7/08 ,  G11C11/4093

Abstract: A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.