公开(公告)号：US20180358088A1

公开(公告)日：2018-12-13

申请号：US16108408

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin YIM ,  Sung-Won YUN ,  Il Han PARK

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.

公开(公告)号：US20230410900A1

公开(公告)日：2023-12-21

申请号：US18238212

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin YIM ,  Sung-Won YUN ,  Il Han PARK

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G06F11/07

CPC classification number: G11C11/5628 ,  G11C16/3459 ,  G11C16/0483 ,  G06F11/0793 ,  G11C16/10

Abstract: A memory device including a first substrate, a peripheral circuit provided on the first substrate, a first metal bonding layer provided on the peripheral circuit, a second metal bonding layer directly bonded to the first metal bonding layer, a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.

公开(公告)号：US20220415388A1

公开(公告)日：2022-12-29

申请号：US17901308

申请日：2022-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin YIM ,  Sung-Won YUN ,  Il Han PARK

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G06F11/07

Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.

公开(公告)号：US20170046210A1

公开(公告)日：2017-02-16

申请号：US15155162

申请日：2016-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin YIM ,  Sung-Won YUN ,  Il Han PARK

IPC: G06F11/07

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.

Abstract translation: 非易失性存储器件的程序验证方法包括执行关于第一级的第一故障位计数操作以产生第一故障位累加值，并将第一故障位累加值和第一故障参考值进行比较以确定程序故障。 当第一故障位累加值小于第一故障参考值时，执行第二级的第二故障位计数操作以产生第二故障位累加值。 将第二故障位累加值与第二参考值进行比较以确定程序故障。 第二个故障参考值与第一个故障参考值不同。