公开(公告)号：US09870950B2

公开(公告)日：2018-01-16

申请号：US15371646

申请日：2016-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Sun Hwang ,  Ja-Eung Koo ,  Jong-Hyung Park ,  Ho-Young Kim ,  Leian Bartolome ,  Bo-Un Yoon ,  Hyoung-Bin Moon

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/28008 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L28/00 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.