公开(公告)号：US11929762B2

公开(公告)日：2024-03-12

申请号：US17878431

申请日：2022-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangseok Lee ,  Geunyeong Yu ,  Youngjun Hwang ,  Hongrak Son ,  Junho Shin ,  Bohwan Jun ,  Hyunseung Han

IPC: H03M13/11

CPC classification number: H03M13/1137 ,  H03M13/112 ,  H03M13/1134

Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

公开(公告)号：US20230163785A1

公开(公告)日：2023-05-25

申请号：US17878431

申请日：2022-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangseok Lee ,  Geunyeong Yu ,  Youngjun Hwang ,  Hongrak Son ,  Junho Shin ,  Bohwan Jun ,  Hyunseung Han

IPC: H03M13/11

CPC classification number: H03M13/1134 ,  H03M13/112

Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

公开(公告)号：US11184030B2

公开(公告)日：2021-11-23

申请号：US16917101

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heeyoul Kwak ,  Jae Hun Jang ,  Hong Rak Son ,  Dong-Min Shin ,  Geunyeong Yu ,  Kangseok Lee ,  Hyunseung Han

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/11 ,  G11C29/42 ,  G06F11/30

Abstract: An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

公开(公告)号：US20210184699A1

公开(公告)日：2021-06-17

申请号：US16917101

申请日：2020-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heeyoul Kwak ,  Jae Hun Jang ,  Hong Rak Son ,  Dong-Min Shin ,  Geunyeong Yu ,  Kangseok Lee ,  Hyunseung Han

IPC: H03M13/15 ,  H03M13/11 ,  G06F11/30 ,  G11C29/42

Abstract: An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

公开(公告)号：US11361832B2

公开(公告)日：2022-06-14

申请号：US16990262

申请日：2020-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunseung Han ,  Seonghyeog Choi ,  Youngsuk Ra ,  Hong Rak Son ,  Taehyun Song ,  Bohwan Jun

IPC: H03M13/29 ,  G06F11/10 ,  G11C16/26 ,  H03M13/11 ,  G06F3/06 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

Abstract: A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.