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    STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE
    1.
    发明申请
    STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE 有权

    公开(公告)号：US20250125820A1

    公开(公告)日：2025-04-17

    申请号：US18628043

    申请日：2024-04-05

    Applicant: SAMSUNG ELECTRONICS CO,. LTD,

    Inventor： Dae-Yeol YANG ,  Dong-Min Shin ,  Bohwan Jun ,  Youngjun Hwang

    IPC: H03M13/11 ,  H03M13/25

    Abstract: A storage device is provided. The storage device includes: a nonvolatile memory device; and a controller configured to: receive first data from the nonvolatile memory device; perform first error correction decoding with respect to the first data to obtain second data; control an error correction capability and an error detection capability of second error correction decoding based on information about the first error correction decoding; and perform the second error correction decoding with respect to the second data based on the error correction capability and the error detection capability to obtain third data.

    Low density parity check decoder and storage device
    2.
    发明授权
    Low density parity check decoder and storage device 有权

    公开(公告)号：US11929762B2

    公开(公告)日：2024-03-12

    申请号：US17878431

    申请日：2022-08-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kangseok Lee ,  Geunyeong Yu ,  Youngjun Hwang ,  Hongrak Son ,  Junho Shin ,  Bohwan Jun ,  Hyunseung Han

    IPC: H03M13/11

    CPC classification number: H03M13/1137 ,  H03M13/112 ,  H03M13/1134

    Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

    Memory controller, operating method of memory controller and memory system
    3.
    发明授权
    Memory controller, operating method of memory controller and memory system 有权

    公开(公告)号：US11037646B2

    公开(公告)日：2021-06-15

    申请号：US16357431

    申请日：2019-03-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minuk Kim ,  Bohwan Jun ,  Hong Rak Son ,  Dong-Min Shin ,  Kijun Lee

    IPC: G11C29/42 ,  G06F11/10 ,  G06F3/06

    Abstract: An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.

    G-LDPC decoder and G-LDPC decoding method
    4.
    发明授权
    G-LDPC decoder and G-LDPC decoding method 有权

    公开(公告)号：US12119841B2

    公开(公告)日：2024-10-15

    申请号：US18141103

    申请日：2023-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Yeol Yang ,  Bohwan Jun ,  Hong Rak Son ,  Geunyeong Yu ,  Youngjun Hwang

    IPC: H03M13/11 ,  H03M13/00

    CPC classification number: H03M13/1111 ,  H03M13/611

    Abstract: a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mth generalized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mth generalized check node from the connected variable nodes; and identify a value of a second message to be provided from the mth generalized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nth variable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.

    Storage device and operating method of storage device
    7.
    发明授权
    Storage device and operating method of storage device 有权

    公开(公告)号：US11361832B2

    公开(公告)日：2022-06-14

    申请号：US16990262

    申请日：2020-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunseung Han ,  Seonghyeog Choi ,  Youngsuk Ra ,  Hong Rak Son ,  Taehyun Song ,  Bohwan Jun

    IPC: H03M13/29 ,  G06F11/10 ,  G11C16/26 ,  H03M13/11 ,  G06F3/06 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

    Abstract: A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.

    Generalized LDPC encoder, generalized LDPC encoding method and storage device
    10.
    发明授权
    Generalized LDPC encoder, generalized LDPC encoding method and storage device 有权

    公开(公告)号：US12255666B2

    公开(公告)日：2025-03-18

    申请号：US18225313

    申请日：2023-07-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daeyeol Yang ,  Bohwan Jun ,  Hongrak Son ,  Geunyeong Yu ,  Youngjun Hwang

    IPC: H03M13/11 ,  H03M13/00 ,  H03M13/13 ,  H03M13/15 ,  H03M13/19

    Abstract: A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and wherein the LDPC encoder is configured to: obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders, determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and output the information bits, the inner parity bits, and the outer parity bits as a codeword.

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