公开(公告)号：US20140099784A1

公开(公告)日：2014-04-10

申请号：US13647577

申请日：2012-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn KIM ,  JE-DON KIM

IPC: H01L21/3205

CPC classification number: H01L27/092 ,  H01L21/02068 ,  H01L21/28088 ,  H01L21/28247 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/0642 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成包括沟槽的绝缘膜，在沟槽中形成第一金属栅极膜图案和第二金属栅极膜图案，在第一和第二金属栅极上再沉积第二金属栅极膜 膜图案和绝缘膜，并且通过执行用于去除一部分再沉积的第二金属栅极膜的平坦化工艺在第一和第二金属栅极膜图案上形成再沉积的第二金属栅极膜图案，以暴露出第二金属栅极膜的顶表面 并且通过氧化再沉积的第二金属栅极膜图案的暴露表面，在再沉积的第二金属栅极膜图案上形成阻挡层图案。

公开(公告)号：US20140227868A1

公开(公告)日：2014-08-14

申请号：US14257466

申请日：2014-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-YOUN KIM ,  HYUN-MIN CHOI ,  SUNG-KEE HAN ,  JE-DON KIM

IPC: H01L21/28 ,  H01L21/285

CPC classification number: H01L21/28008 ,  H01L21/28518 ,  H01L21/823462 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.