公开(公告)号：US20180358055A1

公开(公告)日：2018-12-13

申请号：US16106492

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： REUM OH ,  JE-MIN RYU ,  PAVAN KUMAR KASIBHATLA

IPC: G11C5/02 ,  G11C29/12 ,  G06F12/0893 ,  G11C7/10 ,  G11C29/48 ,  G06F12/084 ,  H01L25/18

CPC classification number: G11C5/02 ,  G06F12/084 ,  G06F12/0893 ,  G11C5/025 ,  G11C7/1006 ,  G11C29/1201 ,  G11C29/48 ,  G11C2207/2245 ,  H01L25/18

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

公开(公告)号：US20190198061A1

公开(公告)日：2019-06-27

申请号：US16293372

申请日：2019-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： REUM OH ,  JE-MIN RYU ,  PAVAN KUMAR KASIBHATLA

IPC: G11C5/02 ,  G06F12/0893 ,  G11C29/12 ,  G11C29/48 ,  G06F12/084 ,  G11C7/10

CPC classification number: G11C5/02 ,  G06F12/084 ,  G06F12/0893 ,  G11C5/025 ,  G11C7/1006 ,  G11C29/1201 ,  G11C29/48 ,  G11C2207/2245 ,  H01L25/18

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

公开(公告)号：US20170358327A1

公开(公告)日：2017-12-14

申请号：US15607699

申请日：2017-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： REUM OH ,  JE-MIN RYU ,  PAVAN KUMAR KASIBHATLA

IPC: G11C5/02 ,  G06F12/0893 ,  G06F12/084 ,  G11C7/10 ,  H01L25/18

CPC classification number: G11C5/02 ,  G06F12/084 ,  G06F12/0893 ,  G11C5/025 ,  G11C7/1006 ,  G11C29/1201 ,  G11C29/48 ,  G11C2207/2245 ,  H01L25/18

Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

公开(公告)号：US20190251043A1

公开(公告)日：2019-08-15

申请号：US16115089

申请日：2018-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-WON PARK ,  JE-MIN RYU ,  SANG-HOON SHIN ,  JAE-HOON JUNG

IPC: G06F13/16 ,  G06F12/0866 ,  G06F12/06

CPC classification number: G06F13/1673 ,  G06F12/0607 ,  G06F12/0866 ,  G06F2212/601

Abstract: A memory device includes a first channel including a first cell array and communicating with a memory controller through a first path, a second channel including a second cell array and communicating with the memory controller through a second path, and an assignment control circuit configured to monitor memory usage of the first and second channels and further assign a storage space of a portion of the second cell array to the first channel when the memory usage of the first cell array exceeds a threshold value. Access to the storage space of the portion of the second cell array assigned to the first channel is performed through the first path.

公开(公告)号：US20130258748A1

公开(公告)日：2013-10-03

申请号：US13835319

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： GIL-SU KIM ,  JONG-MIN OH ,  SUNG-MIN SEO ,  JE-MIN RYU ,  SEONG-JIN JANG

IPC: G11C17/18

CPC classification number: G11C17/18 ,  G11C7/14 ,  G11C17/16 ,  G11C29/789

Abstract: A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.

Abstract translation: 熔丝数据读取电路被配置为以多读取模式读取熔丝数据。 熔丝数据可以存储在包括被配置为存储熔丝数据的多个熔丝单元的熔丝阵列中。 熔丝数据读取电路可以包括感测单元，其被配置为感测存储在熔丝阵列的熔丝单元中的熔丝数据，以及控制器，被配置为控制读取存储在熔丝单元中的熔丝数据的操作。 控制器根据熔丝数据读取操作期间的操作周期设置感测熔丝数据的不同感测条件以读取熔丝数据。 方法包括操作和使用熔丝数据读取电路。