公开(公告)号：US20180122442A1

公开(公告)日：2018-05-03

申请号：US15691985

申请日：2017-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-PIL SON ,  Seong-Il O

IPC: G11C8/08 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C8/08 ,  G11C7/065 ,  G11C7/12 ,  G11C8/18

Abstract: A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. A first word-line, which is selected in response to an access address received from the memory controller, is enabled in response to a first command received from a memory controller, and the first word-line is disabled internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses. The reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and corresponds to a time interval equal to or greater than a row active time interval of the semiconductor memory device.

公开(公告)号：US20180033489A1

公开(公告)日：2018-02-01

申请号：US15730379

申请日：2017-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-PIL SON ,  UK-SONG KANG

IPC: G11C16/10 ,  G06F13/16

CPC classification number: G11C16/102 ,  G06F13/16 ,  G06F13/1673

Abstract: A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.

公开(公告)号：US20170076768A1

公开(公告)日：2017-03-16

申请号：US15264774

申请日：2016-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-PIL SON ,  Uk-Song Kang

IPC: G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: G11C16/102 ,  G06F13/16 ,  G06F13/1673

Abstract: A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.

Abstract translation: 存储器件包括存储单元阵列，数据模式提供单元和写入电路。 存储单元阵列包括多个存储区域。 数据模式提供单元被配置为提供预定义的数据模式。 写入电路被配置为当从外部设备接收到第一写入命令和地址信号时，将从数据模式提供单元提供的预定义数据模式写入与地址信号对应的存储器区域。