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1.发明公开公开(公告)号：US20230205717A1
公开(公告)日：2023-06-29
申请号：US18179052
申请日：2023-03-06
IPC分类号： G06F13/40 , G06F13/364
CPC分类号： G06F13/4004 , G06F13/364 , Y02D10/00
摘要： A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
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公开(公告)号：US11698852B2
公开(公告)日：2023-07-11
申请号：US16913707
申请日：2020-06-26
发明人： Jaeshin Lee , Eunhye Oh , Jaechul Park
CPC分类号： G06F12/0238 , G06F9/30101 , G06F9/30189 , G06F9/544 , G06F11/1451 , G06F11/1469 , G06F12/0891 , G06F13/1673 , G11C7/1039 , G06F2212/1021
摘要： A device for writing data to a memory, the device including: a first write buffer having a first data width that matches a width of write data included in a write request and wherein the first write buffer is configured to store the write data as first data; a second write buffer having a second data width that matches a data width of the memory and is greater than the first data width; and a controller configured to, based on a write address included in the write request and an address of the second data stored in the second write buffer, write the first data stored in the first write buffer to the second write buffer and write the second data stored in the second write buffer to the memory.
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公开(公告)号：US11599491B2
公开(公告)日：2023-03-07
申请号：US17376590
申请日：2021-07-15
IPC分类号： G06F13/364 , G06F13/40
摘要： A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
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公开(公告)号：US10176136B2
公开(公告)日：2019-01-08
申请号：US15899877
申请日：2018-02-20
IPC分类号： G06F13/36 , G06F13/00 , G06F13/40 , G06F13/364
摘要： A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
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公开(公告)号：US11899531B2
公开(公告)日：2024-02-13
申请号：US17563422
申请日：2021-12-28
发明人： Sungwon Jeong , Moonsang Kwon , Younghoi Heo , Jaeshin Lee , Eun Jung
CPC分类号： G06F11/1004 , G06N20/00
摘要： A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a storage controller. The storage controller includes a command and address generator, an error detection module, and an interface circuit. The command and address generator generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address. The error detection module generates the error detection signal from the first command and the address. The interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory. The first command indicates a type of a memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command.
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公开(公告)号：US20220365842A1
公开(公告)日：2022-11-17
申请号：US17563422
申请日：2021-12-28
发明人： Sungwon Jeong , Moonsang Kwon , Younghoi Heo , Jaeshin Lee , Eun Jung
摘要： A storage device and an operating method thereof are provided. The storage device includes a non-volatile memory and a storage controller. The storage controller includes a command and address generator, an error detection module, and an interface circuit. The command and address generator generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address. The error detection module generates the error detection signal from the first command and the address. The interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory. The first command indicates a type of a memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command.
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公开(公告)号：US20210406205A1
公开(公告)日：2021-12-30
申请号：US17211064
申请日：2021-03-24
发明人： Sungwon Jeong , Jinhyuk Lee , Younghoi Heo , Jaeshin Lee
IPC分类号： G06F13/16
摘要： The present disclosure provides a storage system including a first storage device (e.g., a main storage device) and one or more additional storage devices (e.g., sub storage devices). The first storage device includes a host interface for communicating with a host device and is directly connected to the host device. The additional storage devices may be directly connected to the first storage device and may communicate with the host device through the host interface included in the first storage device. The storage system thus has a total combined capacity of both the capacity of the first storage device and the capacity of the one or more additional storage devices. Further, the one or more additional storage devices may be added or removed to increase or decrease the total capacity of the storage system, and the one or more additional storage devices may not necessarily themselves include a host interface.
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公开(公告)号：US11835993B2
公开(公告)日：2023-12-05
申请号：US18179052
申请日：2023-03-06
IPC分类号： G06F13/364 , G06F13/40
CPC分类号： G06F13/4004 , G06F13/364 , Y02D10/00
摘要： A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
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公开(公告)号：US11669470B2
公开(公告)日：2023-06-06
申请号：US17211064
申请日：2021-03-24
发明人： Sungwon Jeong , Jinhyuk Lee , Younghoi Heo , Jaeshin Lee
CPC分类号： G06F13/1668
摘要： The present disclosure provides a storage system including a first storage device (e.g., a main storage device) and one or more additional storage devices (e.g., sub storage devices). The first storage device includes a host interface for communicating with a host device and is directly connected to the host device. The additional storage devices may be directly connected to the first storage device and may communicate with the host device through the host interface included in the first storage device. The storage system thus has a total combined capacity of both the capacity of the first storage device and the capacity of the one or more additional storage devices. Further, the one or more additional storage devices may be added or removed to increase or decrease the total capacity of the storage system, and the one or more additional storage devices may not necessarily themselves include a host interface.
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公开(公告)号：US11080220B2
公开(公告)日：2021-08-03
申请号：US16821289
申请日：2020-03-17
IPC分类号： G06F13/364 , G06F13/40
摘要： A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
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