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11 条记录 (耗时 0.017 秒)

    MEMORY SYSTEM FOR FLEXIBLY ALLOCATING MEMORY FOR MULTIPLE PROCESSORS AND OPERATING METHOD THEREOF
    2.
    发明申请
    MEMORY SYSTEM FOR FLEXIBLY ALLOCATING MEMORY FOR MULTIPLE PROCESSORS AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20210117114A1

    公开(公告)日：2021-04-22

    申请号：US16905305

    申请日：2020-06-18

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Dongsik Cho

    IPC分类号： G06F3/06

    摘要： A memory system includes a memory device that includes a plurality of memory units, a first memory controller that accesses the plurality of memory units, a second memory controller that accesses the plurality of memory units, a memory allocator that, based on set signals, connects a first memory unit of the plurality of memory units to the first memory controller and a second memory unit of the plurality of memory units to the second memory controller, a first processor that uses the first memory unit through the first memory controller, and a second processor that uses the second memory unit through the second memory controller.

    Memory system and SoC including linear addresss remapping logic
    3.
    发明授权
    Memory system and SoC including linear addresss remapping logic 有权
    存储系统和SoC包括线性地址重映射逻辑

    公开(公告)号：US09256531B2

    公开(公告)日：2016-02-09

    申请号：US13803269

    申请日：2013-03-14

    申请人： Samsung Electronics Co., Ltd.

    发明人： Dongsik Cho

    IPC分类号： G06F12/06 ,  G06F12/08

    CPC分类号： G06F3/0634 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F12/0607 ,  G06F12/0646 ,  G06F13/4282 ,  G06F15/781 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

    摘要翻译： 片上系统连接到第一存储设备和第二存储设备。 片上系统包括被配置为控制对第一和第二存储器设备的交织访问操作的存储器控​​制器。 调制解调器处理器被配置为提供用于访问第一或第二存储器设备的地址。 线性地址重映射逻辑被配置为重新映射从调制解调器处理器接收的地址，并将映射的地址提供给存储器控制器。 响应于接收重新映射的地址，存储器控制器对第一或第二存储器设备执行线性访问操作。

    Device and method for sharing resource via bus
    4.
    发明授权
    Device and method for sharing resource via bus 有权

    公开(公告)号：US11914536B2

    公开(公告)日：2024-02-27

    申请号：US17579882

    申请日：2022-01-20

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Dongsik Cho

    IPC分类号： G06F13/362 ,  G06F1/14

    CPC分类号： G06F13/362 ,  G06F1/14

    摘要： The device described herein, which provides an interface between a plurality of master devices and a slave device, includes: a first timer configured to begin timing when a first access request is received from a first master device via a bus, and to be reset when a semaphore is allocated to the first master device; a second timer configured to begin timing when a second access request is received from a second master device via the bus, and to be reset when a semaphore is allocated to the second master device; and a controller configured to provide a first message to the first master device via the bus when a first expiration interval is measured by the first timer.

    Memory system and SoC including linear address remapping logic
    5.
    发明授权
    Memory system and SoC including linear address remapping logic 有权

    公开(公告)号：US11573716B2

    公开(公告)日：2023-02-07

    申请号：US16940687

    申请日：2020-07-28

    申请人： Samsung Electronics Co., Ltd.

    发明人： Dongsik Cho

    IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F15/78 ,  G06F13/42

    摘要： A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller dorms a linear access operation on the first or second memory device in response to receiving the remapped address.

    Integrity check device for safety sensitive data and electronic device including the same
    7.
    发明授权
    Integrity check device for safety sensitive data and electronic device including the same 有权

    公开(公告)号：US11599411B2

    公开(公告)日：2023-03-07

    申请号：US16943185

    申请日：2020-07-30

    申请人： Samsung Electronics Co., Ltd.

    发明人： Dongsik Cho

    IPC分类号： G06F11/10 ,  G06F11/22

    摘要： An integrity check device includes a register array processing circuitry which generates a current cyclic redundancy check (CRC) parity value by sequentially performing a CRC calculation on a plurality of safety sensitive data, stores a reference CRC parity value, outputs a check result signal indicating whether an error occurs by activating a first path and by comparing the current CRC parity value with the reference CRC parity value when the plurality of safety sensitive data are maintained and when an operation of updating the reference CRC parity value is unnecessary, and updates the reference CRC parity value to the current CRC parity value by activating a second path when at least one of the plurality of safety sensitive data is intentionally changed and when the operation of updating the reference CRC parity value is necessary.

    Memory system and SoC including linear address remapping logic
    8.
    发明授权
    Memory system and SoC including linear address remapping logic 有权

    公开(公告)号：US11169722B2

    公开(公告)日：2021-11-09

    申请号：US16215827

    申请日：2018-12-11

    申请人： Samsung Electronics Co., Ltd.

    发明人： Dongsik Cho

    IPC分类号： G06F12/02 ,  G06F3/06 ,  G06F12/06 ,  G06F15/78 ,  G06F13/42

    摘要： A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.