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公开(公告)号：US20240276699A1
公开(公告)日：2024-08-15
申请号：US18536384
申请日：2023-12-12
发明人： Jinseo Choi , Sohyang Lee , Jeongmin Jin , Sohee Choi
IPC分类号： H10B12/00
CPC分类号： H10B12/0335 , H10B12/315 , H10B12/482
摘要： A semiconductor device includes a substrate having an active region; a gate structure in the substrate, crossing the active region, and extending in a first horizontal direction; bit line structures crossing the gate structure and extending in a second horizontal direction, intersecting the first horizontal direction; a contact plug between the bit line structures; a landing pad structure on the contact plug and including a lower landing pad and an upper landing pad on the lower landing pad, wherein the lower landing pad includes a barrier layer and a metal layer on the barrier layer; and an insulating pattern on the lower landing pad and contacting a side surface of the upper landing pad. The upper landing pad is integrally coupled to the metal layer. A side surface of the insulating pattern includes a concave curved surface toward an adjacent bit line structure among the bit line structures.
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公开(公告)号：US20240155832A1
公开(公告)日：2024-05-09
申请号：US18341156
申请日：2023-06-26
发明人： Jinseo Choi , Sohyang Lee , Jeongmin Jin , Sohee Choi
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/0335 , H10B12/315
摘要： An integrated circuit device includes a bit line, an insulating capping pattern on the bit line and having an upper cutout portion, an insulating spacer on sidewalls of the bit line and the insulating capping pattern, a lower contact, a recess contact plug connected to the lower contact, an engraved insulating pattern on the insulating capping pattern and the recess contact plug and having a first portion, a second portion, and an opening, the first portion contacting a top surface of the insulating capping pattern, except for the upper cutout portion, the second portion being on a top surface of the recess contact plug, and the opening being defined by the first portion and the second portion, and a conductive landing pad in the opening of the engraved insulating pattern and having a lower corner portion contacting the upper cutout portion and a surface contacting the recess contact plug.
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公开(公告)号：US12022645B2
公开(公告)日：2024-06-25
申请号：US17398136
申请日：2021-08-10
发明人： Sukhwa Jang , Kanguk Kim , Hyunsuk Noh , Yeongshin Park , Sangkyu Sun , Sunyoung Lee , Sohyang Lee , Hongjun Lee , Hosun Jung , Jeongmin Jin , Jeonghee Choi , Jinseo Choi , Cera Hong
IPC分类号： H10B12/00
CPC分类号： H10B12/0335 , H10B12/053 , H10B12/09 , H10B12/315 , H10B12/34 , H10B12/50
摘要： A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.
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公开(公告)号：US20240196600A1
公开(公告)日：2024-06-13
申请号：US18517917
申请日：2023-11-22
发明人： Jeongmin Jin , Sohyang Lee , Sohee Choi , Jinseo Choi
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/315 , H10B12/50
摘要： A semiconductor memory device includes a substrate including a plurality of active regions in a memory cell region, a plurality of bit line structures extending in parallel with each other in a first horizontal direction in the memory cell region, a plurality of buried contacts respectively and electrically connected to the active regions and partially filling a space between the bit line structures, a plurality of lower landing pads in the space between the bit line structures and respectively on the buried contacts, a landing pad insulating structure in contact with the bit line structures and the lower landing pads and including a plurality of landing pad holes, a plurality of upper landing pads respectively filling the landing pad holes and respectively connected to the lower landing pads, and a plurality of capacitor structures.
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公开(公告)号：US20240155831A1
公开(公告)日：2024-05-09
申请号：US18339299
申请日：2023-06-22
发明人： Jinseo Choi , Sohyang Lee , Jeongmin Jin , Sohee Choi
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/0335 , H10B12/50
摘要： A method of manufacturing an integrated circuit device includes forming, on a substrate, a plurality of bit line structures, which each include a bit line and an insulating capping pattern, and a plurality of contact plugs between the plurality of bit line structures, forming a plurality of recess contact plugs from the plurality of contact plugs and forming a plurality of recess spaces on the plurality of recess contact plugs, forming an engraved insulating pattern having openings, on the plurality of bit line structures and the plurality of recess contact plugs, forming a plurality of cut-off spaces by partially removing the insulating capping pattern of each bit line structure through the openings, and forming a plurality of conductive landing pads to respectively fill the plurality of recess spaces and the plurality of cut-off spaces and respectively contact upper surfaces of the plurality of recess contact plugs.
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