TRANSMITTER, WIRELESS COMMUNICATION MODULE AND POWER AMPLIFICATION SYSTEM

    公开(公告)号:US20250070729A1

    公开(公告)日:2025-02-27

    申请号:US18780949

    申请日:2024-07-23

    Abstract: Disclosed is a transmitter. The transmitter includes a plurality of power amplifiers, each of the plurality of power amplifiers being configured to receive an RF input signal, a parallel power combiner configured to combine outputs of the plurality of power amplifiers to generate an RF output signal, a supply voltage switch configured to provide one supply voltage to the plurality of power amplifiers, the one supply voltage being selected from among a plurality of supply voltages of different voltage levels, and a controller configured to control an output power of the RF output signal by selecting the one supply voltage from among the plurality of supply voltages, and controlling whether to activate each of the plurality of power amplifiers.

    CURRENT-TO-VOLTAGE CONVERTER, TRANSCEIVER, AND WIRELESS COMMUNICATION DEVICE

    公开(公告)号:US20240080060A1

    公开(公告)日:2024-03-07

    申请号:US18230926

    申请日:2023-08-07

    Abstract: The present disclosure provides apparatuses for converting a current signal into a voltage signal. In some embodiments, a current-to-voltage converter includes a transimpedance amplifier, a first filter circuit coupled between an input node of the transimpedance amplifier and an internal node of the transimpedance amplifier, and a second filter circuit coupled between the input node of the transimpedance amplifier and an output node of the transimpedance amplifier. The first filter circuit is configured to operate as a low-pass filter with respect to the current signal. The second filter circuit is configured to operate as a band-pass filter with respect to the current signal. In some embodiments, a transceiver includes a receiver circuit that includes a current-to-voltage converter, a transmitter circuit. The current-to-voltage converter is configured to convert a current signal corresponding to a first reception signal into a voltage signal corresponding to a second reception signal.

    METHOD OF IP2 CALIBRATION FOR WIRELESS TRANSCEIVER AND DEVICE FOR PERFORMING IP2 CALIBRATION

    公开(公告)号:US20250167973A1

    公开(公告)日:2025-05-22

    申请号:US18927234

    申请日:2024-10-25

    Abstract: A device configured to perform second order intercept point (IP2) calibration for a wireless transceiver includes a memory storing instructions, an interface, and at least one processor communicatively coupled to the interface and to the memory. The interface is configured to receive, from the wireless transceiver, a signal including second order intermodulation distortion (IMD2), and transmit, to the wireless transceiver, an in-phase correction code (I-correction code) and a quadrature-phase correction code (Q-correction code). The at least one processor is configured to execute the instructions to analyze a level of the IMD2 based on a plurality of heterogeneous methods, and adjust at least one of the I-correction code or the Q-correction code based on analysis results.

    LOW DROP-OUT REGULATOR AND POWER MANAGEMENT INTEGRATED CIRCUIT INCLUDING THE SAME

    公开(公告)号:US20210397207A1

    公开(公告)日:2021-12-23

    申请号:US17167152

    申请日:2021-02-04

    Abstract: An LDO regulator includes an error amplifier, a power transistor, a monitoring circuit and/or an adaptive pole adjusting circuit (APAC). The error amplifier compares a reference voltage and a feedback voltage to generate a first error voltage based on the comparison. The power transistor including a gate coupled to an output terminal of the buffer, regulates an input voltage based on a second error voltage which is generated based on the first error voltage to provide an output voltage to an output node. The monitoring circuit, connected to the output terminal of the buffer in parallel with the power transistor, generates a control voltage associated with a load current. The APAC, connected between the output terminal of the error amplifier and the ground voltage, selectively connects an adjusting capacitor between the output terminal of the error amplifier and the ground voltage in response to the control voltage.

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