公开(公告)号：US20130262740A1

公开(公告)日：2013-10-03

申请号：US13802748

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JungSik Kim ,  Jungbae Lee

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G11C16/3418 ,  G11C29/24 ,  G11C29/50004 ,  G11C29/52

Abstract: Disclosed is a semiconductor memory device which includes a normal memory cell array; a redundancy memory cell array; and a multi-row selection circuit configured to activate a defective normal memory cell or a defective normal word line of the normal memory cell array while activating a redundancy memory cell or a redundancy word line of the redundancy memory cell array.

Abstract translation: 公开了一种包括正常存储单元阵列的半导体存储器件; 冗余存储单元阵列; 以及多行选择电路，被配置为在激活冗余存储单元阵列的冗余存储单元或冗余字线的同时激活正常存储单元阵列的有缺陷的正常存储单元或缺陷正常字线。

公开(公告)号：US10559550B2

公开(公告)日：2020-02-11

申请号：US16055199

申请日：2018-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungbae Lee ,  Kwanghyun Kim ,  Sang-Kyu Kang ,  Do Kyun Kim ,  DongMin Kim ,  Ji Hyun Ahn

IPC: G11C5/04 ,  H01L25/065 ,  G11C11/4076 ,  H01L23/538 ,  H01L27/108 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/406

Abstract: A memory device includes a first volatile memory chip that includes a first volatile memory cell array storing first data and that receives or outputs the first data at a first bandwidth, and a second volatile memory chip that includes a second volatile memory cell array storing second data and that receives or outputs the second data at a second bandwidth different from the first bandwidth.