公开(公告)号：US20240105856A1

公开(公告)日：2024-03-28

申请号：US18458614

申请日：2023-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyok KO ,  Changsig KANG ,  Junhyeok KIM

IPC: H01L29/861 ,  H01L27/02 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/861 ,  H01L27/0255 ,  H01L27/0296 ,  H01L29/0692 ,  H01L29/417

Abstract: An electrostatic discharge (ESD) device may include a semiconductor substrate, a base well in the semiconductor substrate, a first region including a first impurity region having a first conductivity type within the base well, a second region apart from the first region in a horizontal direction in the base well and including a second impurity region having a second conductivity type a first silicide layer at least partially overlapping the first impurity region in a vertical direction on the first impurity region, and a second silicide layer on the second impurity region and apart from the first silicide layer in the horizontal direction. The second silicide layer may at least partially overlap the second impurity region in the vertical direction. The second conductivity type may be opposite the first conductivity type.

公开(公告)号：US20220376119A1

公开(公告)日：2022-11-24

申请号：US17585284

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyun YOO ,  Kyuok LEE ,  Uihui KWON ,  Junhyeok KIM ,  Yongwoo JEON ,  Dawon JEONG ,  Jaehyok KO

IPC: H01L29/861 ,  H01L29/40 ,  H01L29/06

Abstract: A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.