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公开(公告)号：US20240321381A1
公开(公告)日：2024-09-26
申请号：US18420867
申请日：2024-01-24
发明人： Jiwon SEO , Keeho JUNG
CPC分类号： G11C29/52 , G11C7/106 , G11C7/1069 , G11C7/222
摘要： A memory device including: a memory cell array including pages each page including memory cells; a page buffer circuit including page buffers corresponding to the memory cells of each page, each of the page buffers including first through N-th latches; and a control logic to control first hard decision data and first soft decision data read in a first read operation on a first page to remain in a first page buffer during a second read operation on a second page, and control an output operation such that the first hard decision data is output after the first soft decision data is output when the memory device is set to a first output mode, wherein the first hard decision data is based on a normal read level and the first soft decision data is based on an offset read level read from the first page.
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公开(公告)号：US20230121078A1
公开(公告)日：2023-04-20
申请号：US17954663
申请日：2022-09-28
发明人： Bongkil JUNG , Sangwan NAM , Keeho JUNG
摘要： Provided are a memory device detecting a defect and an operating method thereof. The memory device includes a memory cell area including a memory cell array that stores data, and a peripheral circuit area including a control logic configured to control operations of the memory cell array, wherein the peripheral circuit area further includes a defect detection circuit, the defect detection circuit being configured to generate a count result value by selecting a first input signal from a plurality of input signals and counting at least one time interval of the first input signal based on a clock signal, and to detect a defect of the first input signal by comparing an expected value with the count result value, and the at least one time interval is a length of time in which logic low or logic high is maintained.
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